The DDR memory controller is designed for high efficiency and low latency to support general purpose CPUs following the AXI4 standard, as well as other traditional FPGA applications like video, network buffering, etc.
DDR5 Enhanced Memory Controller
Each SoC device can have multiple DDR5 memory controllers (DDRMC5E or DDRMC5X). The number of memory controllers in a device is specified in the Versal Architecture and Product Data Sheet: Overview (DS950).
The SoC device includes one or more LP/DDR5 enhanced memory controllers (DDRMC5E or DDRMC5X) to provide high efficiency and low latency support for the PS processors and traditional FPGA applications like video, network buffering, etc.
Full-memory encryption is supported with AES-GCM and AES-XTS.
A built-in hardware masking feature is available when using AES-GCM or AES-XTS encryption to provide resistance to DPA or SCA. The DDRMC5E or DDRMC5X controller also includes these features:
- Higher bandwidth
- FUSA requirements and features
- Enhanced calibration features