There are many clocks in the device for clocking logic and I/O. This chapter describes the clocks in the PMC and processing system. This includes clock generators, clock dividers for reference clocks, and the various destinations within the device.
PMC and PS Clocks
The clocks associated with the PMC, processing system, and CPM are described in the following sections:
- The Clock Distribution shows the major internal clocks for the PMC, LPD, and FPD
- Three root clocks originate in the PMC:
- REF_CLK (reference clock input device pin)
- PMC_IRO_CLK (PMC internal ring oscillator)
- RTC (real-time clock)
- There are multiple programmable PLLs and clock dividers in the PMC and processing system for generating clocks in these systems.
NoC, AI Engine, and DDR Memory Controller Clocks
The PMC includes four programmable clock dividers with outputs routed to the PL for general purpose use. The PMC also includes programmable clock divider outputs for the NoC, AI Engine, and DDR memory controllers.
PL Clocks
The PL includes its own clock arrays that are programmed when blocks are instantiated. The PL also includes programmable clock modules that can be driven by clocks from input pins and other sources.
The PMC clock controller includes four sets of reference clock dividers whose output is routed to the PL.
I/O Transceiver Clocks
There are local PLLs in the banks (for the PL, XPHY, and DDRMC) and the gigabit transceivers (GT). These high-speed I/Os use PLL clocks for precision I/O timing. These I/O buffers and transceivers are introduced in the Device I/O Connectivity chapter of the Hardware Architecture section. The I/O transceiver clocks are described in their associated documents:
- GTYP transceiver PLLs: Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)
- X5IO bank XPLLs
Clock Register Modules
The individual clock controls are managed by the PLM firmware. The PLM writes to the clock and reset register modules.