Clock and Reset Registers - Clock and Reset Registers

Clock and Reset Registers - Clock and Reset Registers - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID

AM026

Release Date

2025-12-23

Revision

1.3 English

The USB reference clock and core reset are controlled by the CRL register module. The base address for the CRL register module is 0xFF5E_0000.

Table 1. Clock and Reset Registers for USB
Register Name	Offset Address	Access Type	Description
Reference Clock
USB_LPD_REF_CTRL	`0x0124`	RW	Reference clock control from LPD clock controller
Controller Reset
RST_USB	`0x0314`	RW	Controller reset from LPD reset controller