Clock Tap Control Settings - Clock Tap Control Settings - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)
Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The three clock frequency ranges are shown in the following table.

Table 1. QSPI Clock Tap Delay Settings
Control QSPIx_CLK Frequency Range Register Bit Field
≤ 37.5 MHz >37.5 to 100 MHz >100 to 150 MHz
Data tap delay unit bypass

Bypass
(1)

Bypass
(1)

Enable
(0)

PMC_IOP_SLCR.IOP_TAPDLY_BYPASS [LQSPI_RX]
0: Enabled, use tap delay
1: Bypass
Clock loopback pin enable

Enable
(1)

Enable
(1)

Enable
(1)

LPBK_DLY_ADJ [USE_LPBK]1
0: Disable
1: Enable
Data tap delay settings 00, 000 00, 000 01, 000 LPBK_DLY_ADJ [DLY1], [DLY0]
Data delay enable Disable (0)

Enable
(1)

Disable
(0)

 DATA_DLY_ADJ [USE_DATA_DLY]
Data delay adjustment 000 000 000 DATA_DLY_ADJ [DATA_DLY_ADJ]
  1. During the BootROM phase of the QSPI boot flow, the BootROM runs with clock loopback (QSPI_LPBK_CLK) disabled. For the PLM phase of the QSPI boot flow, the CIPS Wizard enables the QSPI_LPBK_CLK feature by default in the PLM for all QSPIx_CLK frequencies. When the QSPI_LPBK_CLK pin feature is enabled during any phase of boot or QSPI access, the QSPI_LPBK_CLK must be routed to PMC MIO[6], and the PMC MIO[6] pin must be unconnected on the PCB. The QSPI_LPBK_CLK feature is required to be enabled when the QSPIx_CLK frequency is >37.5 MHz. The clock loopback pin can be optionally disabled in the CIPS Wizard only when the QSPIx_CLK frequency is <= 37.5 MHz.
  2. The data delay enable bit is not used when the clock lookback pin is disabled, [USE_LPBK] = 0. However, the data delay enable bit is normally written = 0 when loopback is not used.