Address Generation - Address Generation - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The lower 32 bits of address are generated by the host. The upper address bits have different sources depending on the host. The control of the upper address bits, , includes:

  • Fixed at 0x0
  • Generated by the host
  • Determined by a register setting