Adaptive SoC Interconnect Diagram - Adaptive SoC Interconnect Diagram

Adaptive SoC Interconnect Diagram - Adaptive SoC Interconnect Diagram - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID

AM026

Release Date

2025-12-23

Revision

1.3 English

The following figure shows the device-level hardware architecture and interconnect diagram.

Figure 1. Adaptive SoC Interconnect Architecture

Note: The figure shows an example sets of APUs and RPUs with system caches and on-chip memory. For device-specific features, such as APU cluster configurations, RPU cluster configurations, cache, and on-chip memory details, see the Versal Architecture and Product Data Sheet: Overview (DS950).