AXI Transaction Control - AXI Transaction Control

AXI Transaction Control - AXI Transaction Control - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)

Document ID

AM026

Release Date

2025-12-23

Revision

1.3 English

The AXI transactions generated by the DMA controller can be configured for bufferability and coherency.

Table 1. GEM AXI Transaction Control Registers
LPD Register Name	Offset Address	Access Type	Description
Coherency
GEM0_Coherent GEM1_Coherent	`0x0324` `0x0344`	RW	Select cache coherency policy.
Routing
GEM0_Route GEM1_Route	`0x0328` `0x0348`	RW	Enable transaction to be routed to the FPD coherent interconnect.
QoS
GEM0_QoS GEM1_QoS	`0x032C` `0x034C`	RW	Select QoS bit values.