APU Interconnect Diagram - APU Interconnect Diagram - AM026

The APU subsystem includes the Cortex-A78AE MPCore with the system caches in the cache mesh network (CMN) interconnect. The transactions originating from outside of the APU can be routed to the system memory management unit (SMMU) to allow them access to the APU shared memory and the CMN caches.

The following figure shows the system interconnect. For details on the cache mesh network (CMN), see the figure in Application Processing Unit.

Figure 1. APU Subsystem Interconnect Diagram