The following table lists the APU subsystem units.
| Unit | Description | Links |
|---|---|---|
| Compute Resources | ||
| APU processor | Up to 8-core Cortex-A78AE processor Up to four clusters, 2 cores each 2-core lock-step option v8-architecture 1 |
– |
| APU_A_SWDT APU_B_SWDT APU_C_SWDT APU_D_SWDT |
System watchdog timers (SWDT) for software integrity monitoring | – |
| Interconnect | ||
| AXI interconnect | AXI interconnect switches, NIC-400 | – |
| Coherent mesh network (CMN) | Includes up to four 1 MB system-level caches (SLC) 1 | – |
| SMMU | System memory management unit with translation control unit and several individual translation buffer units (TBU) to translate virtual address into physical address | – |
| Non-coherent interconnect | I/O peripheral switch, and APB programming interface | – |
| FPD_XMPU | Memory protection unit for register and system modules | – |
| FPD_INT_XMPU FPD_CMN_XMPU FPD_SMMU_XMPU FPD_PL_XMPU |
Memory protection units (XMPU) | – |
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