Some Versal devices contain a two-dimensional AI Engine-ML v2 array. Each tile in the array contains: an AI Engine, a high-performance VLIW vector (SIMD) processor; integrated data memory; and interconnects for streaming, configuration, and debug. Alongside the tiles is the AI Engine-ML v2 array interface that provides the necessary logic to connect the AI Engine-ML v2 array to the other resources in the PL, processing system, and the NoC. For devices with the AI Engine-ML v2, the array includes additional rows of 512 KB memory tiles.
See the Versal Architecture and Product Data Sheet: Overview (DS950) for devices that contain an AI Engine-ML v2.
You can access documentation for the AI Engine-ML v2 from the AI Engine Documentation Landing Page (UG1720). For more information about an AI Engine-ML v2 array, see the following:
- AI Engine-ML v2: Versal Adaptive SoC AIE-ML v2 Architecture Manual (AM027)