4 GB Processor System Address Map - 4 GB Processor System Address Map - AM026

Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)
Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English

The 4 GB address map includes 2 GBs for DDR memory and 2 GBs for register modules, local memories, and miscellaneous access ports for the PMC, RPU and APU subsystems. The address space also includes interfaces directly from the PS to the programmable logic (PL). In some devices, the address space defines a cache coherent PCIe® module (CPM) between the PS and a PCIe® -based subsystem.

Table 1. 4 GB Processing System Address Map
Destination Description Type Address Range Size (KB) Firewall
Start End
DDRMC0_Region0_mem DDR Memory Controller 0, Region 0 (lower 2GB less 1 MB) Std mem 0x0000_0000 0x7FDF_FFFF 2046 MB DDRMC0_XMPU
OCM_mem_alias OCM Aliased Regions (all 4 banks) Std mem 0x7FE0_0000 0x7FFF_FFFF 2 MB OCMx_XMPUs
LPD_AXI_PL_mmap LPD to PL AXI Interface Std mmap 0x8000_0000 0x9FFF_FFFF 512 MB LPD_PL_XMPU
PCIe_Region0_mmap PCIe Region 0 (CMN HN-I port) Std mmap 0xA000_0000 0xAFFF_FFFF 256 MB  
FPD_AXI_PL_mmap FPD to PL AXI Interface (dual mode) Std mmap 0xB000_0000 0xB7FF_FFFF 128 MB FPD_PL_XMPU
OCM2_mem OCM Memory Bank 2 Std mem 0xBBE0_0000 0xBBE7_FFFF 512 KB OCM2_XMPU
OCM3_mem OCM Memory Bank 3 Std mem 0xBBE8_0000 0xBBEF_FFFF 512 KB OCM3_XMPU
OCM0_mem OCM Memory Bank 0 Std mem 0xBBF0_0000 0xBBF7_FFFF 512 KB OCM0_XMPU
OCM1_mem OCM Memory Bank 1 Std mem 0xBBF8_0000 0xBBFF_FFFF 512 KB OCM1_XMPU
C2C_Region0_mem C2C Interface (CMN HN-F port) C2C mem 0xBC00_0000 0xBFFF_FFFF 64 MB  
OSPI_mem OSPI flash memory (CMN HN-D port) Std mem 0xC000_0000 0xDFFF_FFFF 512 MB PMC_XPPU (512MB a)
FPD_STM_CoreSight STM CoreSight Std mem 0xE000_0000 0xE0FF_FFFF 16 MB FPD_XMPU
APU_GIC_DIST_MAIN APU GIC Main Distributor Std local 0xE200_0000 0xE20x_FFFF 64 KB FPD_XMPU
APU_GIC_DIST_MB_ALIAS APU GIC MicroBlaze Alias Distributor Std local 0xE201_0000 0xE201_FFFF 64 KB FPD_XMPU
APU_GIC_TRC_DBG APU_GIC_TRC_DBG Std local 0xE202_0000 0xE202_FFFF 64 KB FPD_XMPU
APU_GIC_PMU APU_GIC_PMU Std local 0xE203_0000 0xE203_FFFF 64 KB FPD_XMPU
APU_GIC_ITS_CSR APU_GIC_ITS Control Std local 0xE204_0000 0xE204_FFFF 64 KB FPD_XMPU
APU_GIC_ITS_TRANS APU_GIC_ITS_TRANS Std local 0xE205_0000 0xE205_FFFF 64 KB FPD_XMPU
APU_GIC_REDIST_LPI0 APU GIC redistributor LPI 0 Std local 0xE206_0000 0xE206_FFFF 64 KB FPD_XMPU
APU_GIC_REDIST_SGI0 APU GIC redistributor SGI 0 Std local 0xE207_0000 0xE207_FFFF 64 KB FPD_XMPU
APU_GIC_REDIST_LPI1 APU GIC redistributor LPI 1 Std local 0xE208_0000 0xE208_FFFF 64 KB  
APU_GIC_REDIST_SGI1 APU GIC redistributor SGI 1 Std local 0xE209_0000 0xE209_FFFF 64 KB  
APU_GIC_REDIST_LPI2 APU GIC redistributor LPI 2 Std local 0xE20A_0000 0xE20A_FFFF 64 KB  
APU_GIC_REDIST_SGI2 APU GIC redistributor SGI 2 Std local 0xE20B_0000 0xE20B_FFFF 64 KB  
APU_GIC_REDIST_LPI3 APU GIC redistributor LPI 3 Std local 0xE20C_0000 0xE20C_FFFF 64 KB  
APU_GIC_REDIST_SGI3 APU GIC redistributor SGI 3 Std local 0xE20D_0000 0xE20D_FFFF 64 KB  
APU_GIC_REDIST_LPI4 APU GIC redistributor LPI 4 Std local 0xE20E_0000 0xE20E_FFFF 64 KB  
APU_GIC_REDIST_SGI4 APU GIC redistributor SGI 4 Std local 0xE20F_0000 0xE20F_FFFF 64 KB  
APU_GIC_REDIST_LPI5 APU GIC redistributor LPI 5 Std local 0xE210_0000 0xE210_FFFF 64 KB  
APU_GIC_REDIST_SGI5 APU GIC redistributor SGI 5 Std local 0xE211_0000 0xE211_FFFF 64 KB  
APU_GIC_REDIST_LPI6 APU GIC redistributor LPI 6 Std local 0xE212_0000 0xE212_FFFF 64 KB  
APU_GIC_REDIST_SGI6 APU GIC redistributor SGI 6 Std local 0xE213_0000 0xE213_FFFF 64 KB  
APU_GIC_REDIST_LPI7 APU GIC redistributor LPI 7 Std local 0xE214_0000 0xE214_FFFF 64 KB  
APU_GIC_REDIST_SGI7 APU GIC redistributor SGI 8 Std local 0xE215_0000 0xE215_FFFF 64 KB  
APU_GIC_DIST_ALIAS APU GIC Alias Distributor Std local 0xE216_0000 0xE226_FFFF 64 KB FPD_XMPU
VCU0_SLCR Video controller 0 status and control Std reg 0xE800_0000   256 KB  
VCU0_ENC_0 Video controller 0 analog encoder 0 Std reg 0xE804_0000   4 KB  
VCU0_ENC_1 Video controller 0 analog encoder 1 Std reg 0xE804_1000   4 KB  
VCU0_ENC_2 Video controller 0 analog encoder 2 Std reg 0xE804_2000   4 KB  
VCU0_DEC_0 Video controller 0 analog decoder 0 Std reg 0xE808_0000   4 KB  
VCU0_DEC_1 Video controller 0 analog decoder 1 Std reg 0xE808_1000   768 B  
VCU0_DEC_2 Video controller 0 analog decoder 2 Std reg 0xE808_1300   768 B  
VCU0_DEC_3 Video controller 0 analog decoder 3 Std reg 0xE808_1600   768 B  
VCU0_DEC_4 Video controller 0 analog decoder 4 Std reg 0xE80C_8000   4 KB  
VCU0_DEC_5 Video controller 0 analog decoder 5 Std reg 0xE80C_9000   4 KB  
VCU1_SLCR Video controller 1 status and control Std reg 0xE810_0000   256 KB  
VCU1_ENC_0 Video controller 1 analog encoder 0 Std reg 0xE814_0000   4 KB  
VCU1_ENC_1 Video controller 1 analog encoder 1 Std reg 0xE814_1000   4 KB  
VCU1_ENC_2 Video controller 1 analog encoder 2 Std reg 0xE814_2000   4 KB  
VCU1_DEC_0 Video controller 1 analog decoder 0 Std reg 0xE818_0000   4 KB  
VCU1_DEC_1 Video controller 1 analog decoder 1 Std reg 0xE818_1000   768 B  
VCU1_DEC_2 Video controller 1 analog decoder 2 Std reg 0xE818_1300   768 B  
VCU1_DEC_3 Video controller 1 analog decoder 3 Std reg 0xE818_1600   768 B  
VCU1_DEC_4 Video controller 1 analog decoder 4 Std reg 0xE81C_8000   4 KB  
VCU1_DEC_5 Video controller 1 analog decoder 5 Std reg 0xE81C_9000   4 KB  
ISP0_CSR0 ISP unit 0 MMD tile instance 0 Std reg 0xE850_0000   64 KB  
ISP0_CSR1 ISP unit 0 MMD tile instance 1 Std reg 0xE851_0000   64 KB  
ISP0_IN ISP unit 0 input bus adapter Std reg 0xE852_0000   64 KB  
ISP0_OUT ISP unit 0 output bus adapter Std reg 0xE854_0000   64 KB  
ISP0_GPV ISP unit 0 interconnect global programmers view Std reg 0xE856_0000   64 KB  
ISP0_SLCR ISP unit 0 system-level control registers Std reg 0xE858_0000   64 KB  
ISP0_XMPU ISP unit 0 memory protection unit Std reg 0xE85A_0000   32 KB  
ISP1_CSR0 ISP unit 1 MMD tile instance 0 Std reg 0xE860_0000   64 KB  
ISP1_CSR1 ISP unit 1 MMD tile instance 1 Std reg 0xE861_0000   64 KB  
ISP1_IN ISP unit 1 input bus adapter Std reg 0xE862_0000   64 KB  
ISP1_OUT ISP unit 1 output bus adapter Std reg 0xE864_0000   64 KB  
ISP1_GPV ISP unit 1 interconnect global programmers view Std reg 0xE866_0000   64 KB  
ISP1_SLCR ISP unit 1 system-level control registers Std reg 0xE868_0000   32 KB  
ISP1_XMPU ISP unit 1 memory protection unit Std reg 0xE86A_0000   32 KB  
ISP2_CSR0 ISP unit 2 MMD tile instance 0 Std reg 0xE870_0000   64 KB  
ISP2_CSR1 ISP unit 2 MMD tile instance 1 Std reg 0xE871_0000   64 KB  
ISP2_IN ISP unit 2 input bus adapter Std reg 0xE872_0000   64 KB  
ISP2_OUT ISP unit 2 output bus adapter Std reg 0xE874_0000   64 KB  
ISP2_GPV ISP unit 2 interconnect global programmers view Std reg 0xE876_0000   64 KB  
ISP2_SLCR ISP unit 2 system-level control registers Std reg 0xE878_0000   32 KB  
ISP2_XMPU ISP unit 2 memory protection unit Std reg 0xE87A_0000   32 KB  
LPD_ASIL_D_GPV LPD interconnect ASIL D global programmers view (GPV) Std reg 0xEA40_0000 0xEA40_7FFF 32 KB LPD_XPPU (a4)
LPD_ASIL_B_GPV LPD interconnect ASIL A global programmers view (GPV) Std reg 0xEA40_8000 0xEA40_FFFF 32 KB LPD_XPPU (a4)
OCM_ASIL_D_GPV OCM interconnect ASIL D global programmers view (GPV) Std reg 0xEA41_0000 0xEA41_7FFF 32 KB  
OCM_ASIL_B_GPV OCM interconnect ASIL A global programmers view (GPV) Std reg 0xEA41_8000   32 KB  
RPU_A_SWDT RPU cluster A system watchdog timer (aka SWDT0) Std reg 0xEA42_0000 0xEA42_FFFF 64 KB LPD_XPPU (a4)
RPU_B_SWDT RPU cluster B system watchdog timer Std reg 0xEA43_0000 0xEA43_FFFF 64 KB LPD_XPPU (a4)
RPU_C_SWDT RPU cluster C system watchdog timer Std reg 0xEA44_0000 0xEA44_FFFF 64 KB LPD_XPPU (a4)
RPU_D_SWDT RPU cluster D system watchdog timer Std reg 0xEA45_0000 0xEA45_FFFF 64 KB LPD_XPPU (a4)
LPD_TSG_RO LPD timestamp generator (read-only) Std reg 0xEA46_0000 0xEA46_FFFF 64 KB  
LPD_TSG_RW LPD timestamp generator (read-write) Std reg 0xEA47_0000 0xEA47_FFFF 64 KB  
RPU_E_SWDT RPU cluster E system watchdog timer Std reg 0xEA48_0000 0xEA48_FFFF 64 KB LPD_XPPU (a4)
DPC_DMA Debug packet controller DMA Std reg 0xEA4F_0000 0xEA4F_FFFF 64 KB  
OCM_ASIL_D_INT LPD interconnect ASIL D control and status Std reg 0xEA50_0000   1 MB  
OCM_ASIL_B_INT LPD interconnect ASIL A control and status Std reg 0xEA60_0000   1 MB  
LPD_ASIL_D_INT OCM interconnect ASIL D control and status Std reg 0xEA70_0000   1 MB  
LPD_ASIL_B_INT OCM interconnect ASIL A control and status Std reg 0xEA80_0000   1 MB  
OCM3_CSR OCM bank 3 control and status Std reg 0xEAA0_0000   64 KB  
OCM3_XMPU OCM bank 3 memory protection unit Std reg 0xEAA1_0000   64 KB  
OCM_INT_XMPU OCM interconnect memory protection unit (XMPU) Std reg 0xEAA2_0000   64 KB  
IPI Inter-processor interrupts (IPI) control and status Std reg 0xEB30_0000 0xEB30_FFFF 1 MB LPD_XPPU (a48-a63)
IPI IPI trigger, observation, and interrupt registers Std reg 0xEB31_0000 0xEB31_BFFF 256 KB LPD_XPPU (a48-a63)
OCM0_XMPU OCM bank 0 memory protection unit (XMPU) Std reg 0xEB40_0000 0xEB40_FFFF 64 KB OCM_INT_XMPU
LPD_SLCR LPD system-level control registers Std reg 0xEB41_0000 0xEB50_FFFF 32 KB LPD_XPPU (a65-a80)
LPD_SLCR_SECURE LPD secure system-level control registers Std reg 0xEB51_0000 0xEB54_FFFF 32 KB LPD_XPPU (a81-a84)
LPD_AXI_PL_CSR LPD to PL interface control and status Std reg 0xEB56_0000 0xEB56_7FFF 32 KB LPD_XPPU (a86)
LPD_AXI_PL_GPV LPD to PL interface global programmers view (GPV) Std reg 0xEB56_8000 0xEB56_FFFF 16 KB LPD_XPPU (a86)
LPD_AXI_PL_XMPU LPD to PL interface memory protection unit (XMPU) Std reg 0xEB57_0000 0xEB57_FFFF 16 KB LPD_XPPU (a87)
RPU_A_CSR RPU cluster A control and status Std reg 0xEB58_0000 0xEB58_7FFF 32 KB OCM_INT_XMPU
RPU_A0_CSR RPU cluster A, core 0 control and status Std reg 0xEB58_8000 0xEB58_BFFF 16 KB OCM_INT_XMPU
RPU_A1_CSR RPU cluster A, core 1 control and status Std reg 0xEB58_C000 0xEB58_FFFF 16 KB OCM_INT_XMPU
RPU_B_CSR RPU cluster B control and status Std reg 0xEB59_0000 0xEB59_7FFF 32 KB OCM_INT_XMPU
RPU_B0_CSR RPU cluster B, core 0 control and status Std reg 0xEB59_8000 0xEB59_BFFF 16 KB OCM_INT_XMPU
RPU_B1_CSR RPU cluster B, core 1 control and status Std reg 0xEB59_C000 0xEB59_FFFF 16 KB OCM_INT_XMPU
RPU_C_CSR RPU cluster C control and status Std reg 0xEB5A_0000 0xEB59_7FFF 32 KB OCM_INT_XMPU
RPU_C0_CSR RPU cluster C, core 0 control and status Std reg 0xEB5A_8000 0xEB59_BFFF 16 KB OCM_INT_XMPU
RPU_C1_CSR RPU cluster C, core 1 control and status Std reg 0xEB5A_C000 0xEB59_FFFF 16 KB OCM_INT_XMPU
RPU_D_CSR RPU cluster D control and status Std reg 0xEB5B_0000 0xEB59_7FFF 32 KB OCM_INT_XMPU
RPU_D0_CSR RPU cluster D, core 0 control and status Std reg 0xEB5B_8000 0xEB59_BFFF 16 KB OCM_INT_XMPU
RPU_D1_CSR RPU cluster D, core 1 control and status Std reg 0xEB5B_C000 0xEB59_FFFF 16 KB OCM_INT_XMPU
RPU_E_CSR RPU cluster E control and status Std reg 0xEB5C_0000 0xEB59_7FFF 32 KB OCM_INT_XMPU
RPU_E0_CSR RPU cluster E, core 0 control and status Std reg 0xEB5C_8000 0xEB59_BFFF 16 KB OCM_INT_XMPU
RPU_E1_CSR RPU cluster E, core 1 control and status Std reg 0xEB5C_C000 0xEB59_FFFF 16 KB OCM_INT_XMPU
OCM0_CSR OCM bank 0 control and status Std reg 0xEB5D_0000 0xEB5D_FFFF 64 KB OCM_INT_XMPU
CRL LPD clock and reset control and status Std reg 0xEB5E_0000 0xEB5E_FFFF 64 KB LPD_XPPU (a94-a141)
OCM1_CSR OCM bank 1 control and status Std reg 0xEB96_0000 0xEB96_FFFF 64 KB OCM_INT_XMPU
OCM_TCM_XMPU OCM and TCM memory protection unit (XMPU) Std reg 0xEB97_0000 0xEB97_FFFF 64 KB  
OCM1_XMPU OCM bank 1 memory protection unit (XMPU) Std reg 0xEB98_0000 0xEB98_FFFF 64 KB OCM_INT_XMPU
LPD_XPPU LPD peripheral protect unit to control and status registers Std reg 0xEB99_0000 0xEB99_FFFF 64 KB LPD_XPPU (a153)
RPU_GIC RPU interrupt controller (GIC-390) Std reg 0xEB9A_0000 0xEB9A_FFFF 64 KB Local access only
PL_AXI_LPD_CSR PL to LPD AXI/ACE interface control and status Std reg 0xEB9B_0000 0xEB9B_FFFF 64 KB LPD_XPPU (a155)
DPC_AURORA_CSR Aurora unit control and status Std reg 0xEB9C_0000 0xEB9C_FFFF 64 KB LPD_XPPU (a156)
OCM2_CSR OCM bank 2 control and status Std reg 0xEB9D_0000 0xEB9D_FFFF 64 KB  
OCM2_XMPU OCM bank 2 memory protection unit (XMPU) Std reg 0xEB9E_0000 0xEB9E_FFFF 64 KB  
RPU_A0_TCM_A RPU A0 TCM A dual mode and lockstep mode Std mem 0xEBA0_0000 0xEBA0_FFFF 64 KB OCM_INT_XMPU
RPU_A0_TCM_B RPU A0 TCM B dual mode and lockstep mode Std mem 0xEBA1_0000 0xEBA1_7FFF 32 KB OCM_INT_XMPU
RPU_A0_TCM_C RPU A0 TCM C dual mode and lockstep mode Std mem 0xEBA2_0000 0xEBA2_7FFF 32 KB OCM_INT_XMPU
RPU_A1_TCM_A RPU A1 TCM A dual mode only Std mem 0xEBA4_0000 0xEBA4_FFFF 64 KB OCM_INT_XMPU
RPU_A1_TCM_B RPU A1 TCM B dual mode only Std mem 0xEBA5_0000 0xEBA5_7FFF 32 KB OCM_INT_XMPU
RPU_A1_TCM_C RPU A1 TCM C dual mode only Std mem 0xEBA6_0000 0xEBA6_7FFF 32 KB OCM_INT_XMPU
RPU_B0_TCM_A RPU B0 TCM A dual mode and lockstep mode Std mem 0xEBA8_0000 0xEBA8_FFFF 64 KB OCM_INT_XMPU
RPU_B0_TCM_B RPU B0 TCM B dual mode and lockstep mode Std mem 0xEBA9_0000 0xEBA9_7FFF 32 KB OCM_INT_XMPU
RPU_B0_TCM_C RPU B0 TCM C dual mode and lockstep mode Std mem 0xEBAA_0000 0xEBAA_7FFF 32 KB OCM_INT_XMPU
RPU_B1_TCM_A RPU B1 TCM A dual mode only Std mem 0xEBAC_0000 0xEBAC_FFFF 64 KB OCM_INT_XMPU
RPU_B1_TCM_B RPU B1 TCM B dual mode only Std mem 0xEBAD_0000 0xEBAD_7FFF 32 KB OCM_INT_XMPU
RPU_B1_TCM_C RPU B1 TCM C dual mode only Std mem 0xEBAE_0000 0xEBAE_7FFF 32 KB OCM_INT_XMPU
RPU_C0_TCM_A RPU C0 TCM A dual mode and lockstep mode Std mem 0xEBB0_0000 0xEBB0_FFFF 64 KB OCM_INT_XMPU
RPU_C0_TCM_B RPU C0 TCM B dual mode and lockstep mode Std mem 0xEBB1_0000 0xEBB1_7FFF 32 KB OCM_INT_XMPU
RPU_C0_TCM_C RPU C0 TCM C dual mode and lockstep mode Std mem 0xEBB2_0000 0xEBB2_7FFF 32 KB OCM_INT_XMPU
RPU_C1_TCM_A RPU C1 TCM A dual mode only Std mem 0xEBB4_0000 0xEBB4_FFFF 64 KB OCM_INT_XMPU
RPU_C1_TCM_B RPU C1 TCM B dual mode only Std mem 0xEBB5_0000 0xEBB5_7FFF 32 KB OCM_INT_XMPU
RPU_C1_TCM_C RPU C1 TCM C dual mode only Std mem 0xEBB6_0000 0xEBB6_7FFF 32 KB OCM_INT_XMPU
RPU_D0_TCM_A RPU D0 TCM A dual mode and lockstep mode Std mem 0xEBB8_0000 0xEBB8_FFFF 64 KB OCM_INT_XMPU
RPU_D0_TCM_B RPU D0 TCM B dual mode and lockstep mode Std mem 0xEBB9_0000 0xEBB9_7FFF 32 KB OCM_INT_XMPU
RPU_D0_TCM_C RPU D0 TCM C dual mode and lockstep mode Std mem 0xEBBA_0000 0xEBBA_7FFF 32 KB OCM_INT_XMPU
RPU_D1_TCM_A RPU D1 TCM A dual mode only Std mem 0xEBBC_0000 0xEBBC_FFFF 64 KB OCM_INT_XMPU
RPU_D1_TCM_B RPU D1 TCM B dual mode only Std mem 0xEBBD_0000 0xEBBD_7FFF 32 KB OCM_INT_XMPU
RPU_D1_TCM_C RPU D1 TCM C dual mode only Std mem 0xEBBE_0000 0xEBBE_7FFF 32 KB OCM_INT_XMPU
RPU_E0_TCM_A RPU E0 TCM A dual mode and lockstep mode Std mem 0xEBC0_0000 0xEBC0_FFFF 64 KB OCM_INT_XMPU
RPU_E0_TCM_B RPU E0 TCM B dual mode and lockstep mode Std mem 0xEBC1_0000 0xEBC1_7FFF 32 KB OCM_INT_XMPU
RPU_E0_TCM_C RPU E0 TCM C dual mode and lockstep mode Std mem 0xEBC2_0000 0xEBC2_7FFF 32 KB OCM_INT_XMPU
RPU_E1_TCM_A RPU E1 TCM A dual mode only Std mem 0xEBC4_0000 0xEBC4_FFFF 64 KB OCM_INT_XMPU
RPU_E1_TCM_B RPU E1 TCM B dual mode only Std mem 0xEBC5_0000 0xEBC5_7FFF 32 KB OCM_INT_XMPU
RPU_E1_TCM_C RPU E1 TCM C dual mode only Std mem 0xEBC6_0000 0xEBC6_7FFF 32 KB OCM_INT_XMPU
LPD_DMA0_CH0 LPD general purpose DMA controller 0, ch 0 Std reg 0xEBD0_0000 0xEBD0_FFFF 64 KB  
LPD_DMA0_CH1 LPD general purpose DMA controller 0, ch 1 Std reg 0xEBD1_0000 0xEBD1_FFFF 64 KB  
LPD_DMA0_CH2 LPD general purpose DMA controller 0, ch 2 Std reg 0xEBD2_0000 0xEBD2_FFFF 64 KB  
LPD_DMA0_CH3 LPD general purpose DMA controller 0, ch 3 Std reg 0xEBD3_0000 0xEBD3_FFFF 64 KB  
LPD_DMA0_CH4 LPD general purpose DMA controller 0, ch 4 Std reg 0xEBD4_0000 0xEBD4_FFFF 64 KB  
LPD_DMA0_CH5 LPD general purpose DMA controller 0, ch 5 Std reg 0xEBD5_0000 0xEBD5_FFFF 64 KB  
LPD_DMA0_CH6 LPD general purpose DMA controller 0, ch 6 Std reg 0xEBD6_0000 0xEBD6_FFFF 64 KB  
LPD_DMA0_CH7 LPD general purpose DMA controller 0, ch 7 Std reg 0xEBD7_0000 0xEBD7_FFFF 64 KB  
LPD_DMA1_CH0 LPD general purpose DMA controller 1, ch 0 Std reg 0xEBD8_0000 0xEBD8_FFFF 64 KB  
LPD_DMA1_CH1 LPD general purpose DMA controller 1, ch 1 Std reg 0xEBD9_0000 0xEBD9_FFFF 64 KB  
LPD_DMA1_CH2 LPD general purpose DMA controller 1, ch 2 Std reg 0xEBDA_0000 0xEBDA_FFFF 64 KB  
LPD_DMA1_CH3 LPD general purpose DMA controller 1, ch 3 Std reg 0xEBDB_0000 0xEBDB_FFFF 64 KB  
LPD_DMA1_CH4 LPD general purpose DMA controller 1, ch 4 Std reg 0xEBDC_0000 0xEBDC_FFFF 64 KB  
LPD_DMA1_CH5 LPD general purpose DMA controller 1, ch 5 Std reg 0xEBDD_0000 0xEBDD_FFFF 64 KB  
LPD_DMA1_CH6 LPD general purpose DMA controller 1, ch 6 Std reg 0xEBDE_0000 0xEBDE_FFFF 64 KB  
LPD_DMA1_CH7 LPD general purpose DMA controller 1, ch 7 Std reg 0xEBDF_0000 0xEBDF_FFFF 64 KB  
ASU_RAM_INSTR ASU processor instruction cache Std mem 0xEBE0_0000 0xEBE3_FFFF 256 KB  
ASU_RAM_DATA ASU processor data cache Std mem 0xEBE4_0000 0xEBE5_FFFF 128 KB  
ASU_IO_BUS ASU I/O bus Std reg 0xEBE8_0000 0xEBE7_FFFF 32 KB  
ASU_AES ASU AES security unit Std reg 0xEBE8_8000 0xEBE8_7FFF 8 KB  
ASU_KEY ASU Key security unit Std reg 0xEBE8_A000 0xEBE8_9FFF 8 KB  
ASU_DMA0 ASU DMA controller 0 Std reg 0xEBE8_C000 0xEBE8_BFFF 4 KB  
ASU_DMA1 ASU DMA controller 1 Std reg 0xEBE8_D000 0xEBE8_CFFF 4 KB  
ASU_LOCAL ASU local registers Std reg 0xEBE8_E000 0xEBE8_DFFF 8 KB  
ASU_RAM_INSTR_ECC_CTRL ASU processor instruction cache ECC control Std reg 0xEBEA_0000 0xEBEA_FFFF 64 KB  
ASU_RAM_DATA_ECC_CTRL ASU processor data cache ECC control Std reg 0xEBEB_0000 0xEBEB_FFFF 64 KB  
ASU_TMR_MANAGER ASU processor TMR manager Std reg 0xEBEC_0000 0xEBEC_FFFF 64 KB  
ASU_TMR_INJECT ASU processor TMR error injection registers Std reg 0xEBED_0000 0xEBED_FFFF 64 KB  
ASU_TMR_TRACE ASU processor TMR trace Std reg 0xEBEE_0000 0xEBEE_FFFF 64 KB  
ASU_MDM ASU processor triple redundancy trace Std reg 0xEBEF_0000 0xEBF0_FFFF 64 KB  
ASU_ECC ASU processor debug interface Std reg 0xEBF0_0000 0xEBF1_FFFF 64 KB  
ASU_TRNG_AXI ASU true random number generator interface Std reg 0xEBF1_0000 0xEBF2_FFFF 64 KB  
ASU_TRNG ASU true random number generator control and status Std reg 0xEBF2_0000 0xEBF3_FFFF 64 KB  
ASU_SHA2 ASU SHA2 unit Std reg 0xEBF3_0000 0xEBF4_FFFF 64 KB  
ASU_SHA3 ASU SHA3 unit Std reg 0xEBF4_0000 0xEBF5_FFFF 64 KB  
ASU_RSA ASU RSA unit Std reg 0xEBF5_0000 0xEBF6_FFFF 64 KB  
ASU_INT_CSR ASU interconnect control and status Std reg 0xEBF7_0000 0xEBF7_EFFF 60 KB  
ASU_INT_GPV ASU interconnect global programmers view Std reg 0xEBF7_F000 0xEBF7_FFFF 4 KB  
ASU_GLOBAL ASU global registers Std reg 0xEBF8_0000 0xEBF9_FFFF 128 KB  
ASU_PL_CSR ASU-PL interface control and status Std reg 0xEBFC_0000 0xEBFF_FFFF 256 KB  
FPD_SMMU_TBU_CSR FPD SMMU TCU and TBU control and status Std reg 0xEC00_0000 0xEBF9_FFFF 2 MB FPD_SMMU_XMPU
CRF FPD Clock and Reset Controller Std reg 0xEC20_0000 0xEBFB_FFFF 1 MB FPD_XMPU
PS_SPLIT_CSR PS Interconnect splitter control and status Std reg 0xEC30_0000 0xEB_FFFFFF 1 MB  
FPD_ASIL_D_INT FPD ASIL D control and status Std reg 0xEC40_0000   1 MB  
FPD_ASIL_B_INT FPD ASIL B control and status Std reg 0xEC50_0000   1 MB  
FPD_NOC_1_INT FPD NoC 1 control and status Std reg 0xEC60_0000   512 KB  
FPD_NOC_0_INT FPD NoC 0 control and status Std reg 0xEC68_0000   512 KB  
MMI_NOC_INT MMI NoC control and status Std reg 0xEC70_0000   512 KB  
MMI_NOC_GPV MMI NoC global programmers view Std reg 0xEC7F_4000   16 KB  
FPD_NOC_0_GPV FPD NoC 0 global programmers view Std reg 0xEC7F_8000   16 KB  
FPD_NOC_1_GPV FPD NoC 1 global programmers view Std reg 0xEC7F_C000   16 KB  
FPD_INT_GPV FPD interconnect switch global programmers view (GPV) Std reg 0xEC80_0000 0xEC80_0FFF 16 KB FPD_XMPU
FPD_CPM5N_GPV FPD-CPM5N global programmers view (GPV) Std reg 0xEC80_4000 0xEC80_4FFF 16 KB FPD_XMPU
OCM_SPLIT_GPV OCM splitter global programmers view (GPV) Std reg 0xEC80_8000 0xEC80_8FFF 16 KB FPD_XMPU
FPD_INT_ASIL_D_XMPU FPD interconnect ASIL D memory protection unit Std reg 0xEC81_0000   16 KB  
FPD_INT_ASIL_B_XMPU FPD interconnect ASIL B memory protection unit Std reg 0xEC82_0000   16 KB  
FPD_CMN_XMPU FPD CMN memory protection unit (XMPU) Std reg 0xEC83_0000 0xEC83_FFFF 64 KB FPD_XMPU
FPD_SMMU_XMPU FPD SMMU memory protection unit Std reg 0xEC84_0000 0xEC84_FFFF 64 KB FPD_XMPU
FPD_AXI_PL_CSR FPD to PL AXI interface control and status Std reg 0xEC86_0000 0xEC86_FFFF 32 KB FPD_XMPU
FPD_AXI_PL_GPV FPD to PL AXI interconnect global programmers view (GPV) Std reg 0xEC86_8000 0xEC86_80x0 32 KB FPD_XMPU
FPD_PL_XMPU FPD to PL AXI interface memory protection unit (XMPU) Std reg 0xEC87_0000 0xEC87_FFFF 64 KB FPD_XMPU
PL_AXI0_FPD_CSR PL to FPD APU cluster B port, interface 0 Std reg 0xEC88_0000 0xEC88_FFFF 64 KB FPD_XMPU
PL_AXI1_FPD_CSR PL to FPD APU cluster B port, interface 1 Std reg 0xEC89_0000 0xEC89_FFFF 64 KB FPD_XMPU
PL_AXI2_FPD_CSR PL to FPD APU cluster C port, interface 0 Std reg 0xEC8A_0000 0xEC8A_FFFF 64 KB FPD_XMPU
PL_AXI3_FPD_CSR PL to FPD APU cluster C port, interface 1 Std reg 0xEC8B_0000 0xEC8B_FFFF 64 KB FPD_XMPU
FPD_SLCR FPD System Level control and status Std reg 0xEC8C_0000 0xEC8C_FFFF 64 KB FPD_XMPU
FPD_SLCR_SECURE FPD System Level secure control and status Std reg 0xEC8E_0000 0xEC8E_FFFF 64 KB FPD_XMPU
FPD_EVENT_CSR FPD Event control and status Std reg 0xEC90_0000 0xEC90_FFFF 64 KB FPD_XMPU
FPD_TSG_RO FPD timestamp generator (read-only) Std reg 0xEC91_0000 0xEC91_FFFF 64 KB FPD_XMPU
FPD_TSG_RW FPD timestamp generator (read-write) Std reg 0xEC92_0000 0xEC92_FFFF 64 KB FPD_XMPU
FPD_CMN_CSR FPD CMN control and status Std reg 0xECA0_0000 0xECA0_FFFF 64 KB FPD_XMPU
FPD_SMMU_CSR FPD SMMU core control and status Std reg 0xECA1_0000 0xECA1_FFFF 64 KB FPD_XMPU
FPD_SMMU_FMU   Std reg 0xECA2_0000 0xECA2_FFFF 64 KB FPD_SMMU_XMPU
APU_GIC_FMU APU GIC Fault Management Unit Std reg 0xECB0_0000 0xECB0_FFFF 64 KB FPD_XMPU
APU_PCIL APU power control interface logic Std reg 0xECB1_0000 0xECB1_FFFF 64 KB FPD_XMPU
APU_A_CSR APU cluster A control and status Std reg 0xECC0_0000 0xECC0_FFFF 64 KB FPD_XMPU
APU_A_SWDT APU cluster A system watchdog timer (aka SWDT1) Std reg 0xECC1_0000 0xECC1_FFFF 64 KB FPD_XMPU
PS_SPLIT_0 PS data splitter 0 to NoC Std reg 0xECC2_0000 0xECC2_FFFF 64 KB FPD_XMPU
APU_B_CSR APU cluster B control and status Std reg 0xECD0_0000 0xECD0_FFFF 64 KB FPD_XMPU
APU_B_SWDT APU cluster B system watchdog timer Std reg 0xECD1_0000 0xECD1_FFFF 64 KB FPD_XMPU
PS_SPLIT_1 PS data splitter 1 to NoC Std reg 0xECD2_0000 0xECD2_FFFF 64 KB FPD_XMPU
APU_C_CSR APU cluster C control and status Std reg 0xECE0_0000 0xECE0_FFFF 64 KB FPD_XMPU
APU_C_SWDT APU cluster C system watchdog timer Std reg 0xECE1_0000 0xECE1_FFFF 64 KB FPD_XMPU
PS_SPLIT_2 PS data splitter 2 to NoC Std reg 0xECE2_0000 0xECE2_FFFF 64 KB FPD_XMPU
APU_D_CSR APU cluster D control and status Std reg 0xECF0_0000 0xECF0_FFFF 64 KB FPD_XMPU
APU_D_SWDT APU cluster D system watchdog timer Std reg 0xECF1_0000 0xECF1_FFFF 64 KB FPD_XMPU
PS_SPLIT_3 PS data splitter 3 to NoC Std reg 0xECF2_0000 0xECF2_FFFF 64 KB FPD_XMPU
MMI_GPU_SLCR MMI GPU system-level control registers Std reg 0xED72_0000   8 KB  
MMI_GPU_SLCR_SECURE MMI GPU secure system-level control registers Std reg 0xED72_2000   8 KB  
MMI_PCIE0_CTRL_USP MMI PCIe 0 Control USP Std reg 0xED80_0000   256 KB  
MMI_PCIE0_CTRL_DSP MMI PCIe 0 Control DSP Std reg 0xED84_0000   256 KB  
MMI_PCIE1_CTRL_USP MMI PCIe 1 Control USP Std reg 0xED88_0000   256 KB  
MMI_PCIE1_CTRL_DSP MMI PCIe 1 Control DSP Std reg 0xED8C_0000   256 KB  
MMI_PCIEGEM_10GBE MMI 10GbE Std reg 0xED92_0000   64 KB  
MMI_PIPE_GEM_SLCR MMI PIPE and 10GbE IO SLCR Std reg 0xED93_0000   4 KB  
MMI_PCIE0_CTRL_SLCR MMI PCIe 0 system-level control Std reg 0xED93_1000   32 KB  
MMI_PCIE1_CTRL_SLCR MMI PCIe 1 system-level control Std reg 0xED93_9000   32 KB  
MMI_INT_CONFIG MMI interconnect configuration Std reg 0xEDA0_0000   2 MB  
MMI_CRX MMI clock and reset control Std reg 0xEDC0_0000   64 KB  
MMI_SYSMON MMI system monitor Std reg 0xEDC1_0000   64 KB  
MMI_SLCR MMI system-level control registers Std reg 0xEDC2_0000   64 KB  
MMI_SLCR_SECURE MMI secure system-level control registers Std reg 0xEDC3_0000   64 KB  
MMI_XMPU MMI memory protection unit Std reg 0xEDC6_0000   64 KB  
MMI_PRAM_CFG MMI PRAM configuration Std reg 0xEDC7_0000   64 KB  
MMI_DP MMI DP Std reg 0xEDD0_0000   32 KB  
MMI_DC MMI DC Std reg 0xEDD0_8000   32 KB  
MMI_DPDMA MMI DP DMA configuration Std reg 0xEDD1_0000   32 KB  
MMI_UDH_DP MMI UDH DP Std reg 0xEDE0_0000   256 KB  
MMI_UDH_USB3PHY_CRPARA MMI UDH USB3 phy clock parameters Std reg 0xEDE4_0000   256 KB  
MMI_UDH_TRNG_CFG MMI UDH TRNG configuration Std reg 0xEDE8_0000   64 KB  
MMI_UDH_PLL MMI UDH PLL configuration Std reg 0xEDE9_0000   64 KB  
MMI_UDH_SLCR MMI UDH system-level control registers Std reg 0xEDEA_0000   64 KB  
MMI_UDH_HDCP MMI UDH HDCP Std reg 0xEDEB_0000   32 KB  
MMI_UDH_USB3PHY_TCA MMI UDH USB3 phy TCA parameters Std reg 0xEDEB_8000   16 KB  
MMI_UDH_USB2PHY MMI UDH USB3 phy parameters Std reg 0xEDEB_C000   16 KB  
MMI_USB_CFG MMI USB configuration Std reg 0xEDEC_0000   64 KB  
PMC_LOCAL PMC Local processor registers (info provided under NDA) NDA reg 0xF004_0000 0xF0x4_FFFF 64 KB  
PMC_PUF PMC PUF registers (info provided under NDA) NDA reg 0xF005_0000 0xF0x5_FFFF 64 KB  
PPU_RAM_INSTR PPU RAM for PLM Firmware Instruction Execution Std mem 0xF020_0000 0xF027_FFFF 512 KB PMC_XPPU (1MB a2)
PPU_RAM_DATA PPU RAM for PLM Firmware Data Std mem 0xF028_0000 0xF029_FFFF 128 KB PMC_XPPU (1MB a2)
PPU_IOMODULE PPU I/O Module registers Std reg 0xF030_0000 0xF030_0FFF 4 KB  
PPU_ICACHE0_CTRL PPU I-cache 0 ECC control Std reg 0xF030_1000 0xF030_1FFF 4 KB  
PPU_DCACHE_CTRL PPU D-cache ECC control Std reg 0xF030_2000 0xF030_2FFF 4 KB  
PPU_TMR_MANAGER PPU Triple Redundancy Manager Std reg 0xF030_3000 0xF030_3FFF 4 KB  
PPU_TMR_INJECT PPU Triple Redundancy Error Injection Std reg 0xF030_4000 0xF030_4FFF 4 KB  
PPU_ICACHE1_CTRL PPU I-cache 1 ECC control Std reg 0xF030_5000 0xF030_5FFF 4 KB  
PPU_TMR_TRACE PPU Trace Module control Std reg 0xF030_6000 0xF030_6FFF 4 KB  
PPU_MDM PPU Debug Module control Std reg 0xF031_0000 0xF031_7FFF 32 KB PMC_XPPU (1MB a3)
PMC_SWDT PMC system watchdog timer Std reg 0xF03F_0000 0xF03F_3FFF 64 KB  
CoreSight Registers CoreSight Registers in LPD Std reg 0xF080_0000 0xF0FF_FFFF ~8MB PMC_XPPU (1MB a8)
PMC_I3C PMC I3C registers Std reg 0xF100_0000 0xF10x_FFFF 64 KB  
OSPI OSPI controller Std reg 0xF101_0000 0xF101_FFFF 64 KB  
PMC_GPIO PMC GPIO controller Std reg 0xF102_0000 0xF102_FFFF 64 KB  
QSPI Quad-SPI controller Std reg 0xF103_0000 0xF103_FFFF 64 KB  
SD SD_eMMC v4.51 controller Std reg 0xF104_0000 0xF104_FFFF 64 KB  
EMMC SDIO eMMC v5.1 controller Std reg 0xF105_0000 0xF105_FFFF 64 KB  
PMC_IOP_SLCR PMC IOP system level control Std reg 0xF106_0000 0xF106_FFFF 64 KB  
PMC_IOP_SLCR_SECURE PMC IOP secure system level control Std reg 0xF107_0000 0xF107_FFFF 64 KB  
PMC_IOP_INT_GPV PMC IOP interconnect global programmers view (GPV) Std reg 0xF108_0000 0xF108_FFFF 64 KB  
PMC_IOP_INT_CSR PMC IOP interconnect control and status Std reg 0xF109_0000   64 KB  
UFS_XHCI Universal flash storage XHCI control and status Std reg 0xF10B_0000   64 KB  
PMC_RAM_CSR PMC RAM control and status (info partially provided under NDA) pNDA reg 0xF110_0000 0xF110_FFFF 64 KB  
PMC_GLOBAL PMC global registers Std reg 0xF111_0000 0xF115_FFFF 320 KB  
PMC_ANLG PMC analog voltage monitoring registers pNDA reg 0xF116_0000 0xF119_FFFF 256 KB  
PMC_JTAG_CSR PMC JTAG TAP registers Std reg 0xF11A_0000 0xF11B_FFFF 128 KB  
PMC_DMA0_CSR PMC DMA registers Std reg 0xF11C_0000 0xF11C_FFFF 64 KB  
PMC_DMA1_CSR PMC DMA registers Std reg 0xF11D_0000 0xF11D_FFFF 64 KB  
PMC_AES AES registers NDA reg 0xF11E_0000 0xF11E_FFFF 64 KB  
PMC_BBRAM_CTRL Battery-backed RAM Control registers NDA reg 0xF11F_0000 0xF11F_FFFF 64 KB  
PMC_ECDSA_RSA RSA and ECC Control/Status registers NDA reg 0xF120_0000 0xF120_FFFF 64 KB  
PMC_SHA3 SHA v3 controller 0 NDA reg 0xF121_0000 0xF121_FFFF 64 KB  
PMC_SBI_CSR Slave Boot Interface registers Std reg 0xF122_0000 0xF122_FFFF 64 KB  
PMC_TRNG True Random Number Generator control and status NDA reg 0xF123_0000 0xF123_FFFF 64 KB  
PMC_EFUSE_CTRL eFuse control and status pNDA reg 0xF124_0000 0xF124_FFFF 64 KB  
PMC_EFUSE_CACHE eFuse cache data pNDA reg 0xF125_0000 0xF125_FFFF 64 KB  
CRP Clock and Reset control and status Std reg 0xF126_0000 0xF126_FFFF 64 KB  
PMC_SYSMON System Monitor control and status Std reg 0xF127_0000 0xF129_FFFF 192 KB  
PMC_RTC RTC control and status Std reg 0xF12A_0000 0xF12A_FFFF 64 KB  
CFU_CSR Configuration Frame Unit (CFU) control and status Std reg 0xF12B_0000 0xF12B_FFFF 64 KB  
CFU_STREAM_port CFU stream Std port 0xF12C_0000 0xF12C_0FFF 4 KB  
CFU_SFR CFU single frame read register Std port 0xF12C_1000 0xF12C_1FFF 4 KB  
CFU_FDRO CFU frame data register output (FDRO) Std port 0xF12C_2000 0xF12C_2FFF 4 KB  
CFRAME00_REG CFU frame 0 control and status Std reg 0xF12D_0000 0xF12D_0FFF 4 KB  
CFRAME00_FDRI CFU frame 0 data register input (FDRI) Std port 0xF12D_1000 0xF12D_1FFF 4 KB  
CFRAME01_REG CFU frame 1 control and status Std reg 0xF12D_2000 0xF12D_2FFF 4 KB  
CFRAME01_FDRI CFU frame 1 data register input (FDRI) Std port 0xF12D_3000 0xF12D_3FFF 4 KB  
CFRAME02_REG CFU frame 2 control and status Std reg 0xF12D_4000 0xF12D_4FFF 4 KB  
CFRAME02_FDRI CFU frame 2 data register input (FDRI) Std port 0xF12D_5000 0xF12D_5FFF 4 KB  
CFRAME03_REG CFU frame 3 control and status Std reg 0xF12D_6000 0xF12D_6FFF 4 KB  
CFRAME03_FDRI CFU frame 3 data register input (FDRI) Std port 0xF12D_7000 0xF12D_7FFF 4 KB  
CFRAME04_REG CFU frame 4 control and status Std reg 0xF12D_8000 0xF12D_8FFF 4 KB  
CFRAME04_FDRI CFU frame 4 data register input (FDRI) Std port 0xF12D_9000 0xF12D_9FFF 4 KB  
CFRAME05_REG CFU frame 5 control and status Std reg 0xF12D_A000 0xF12D_AFFF 4 KB  
CFRAME05_FDRI CFU frame 5 data register input (FDRI) Std port 0xF12D_B000 0xF12D_BFFF 4 KB  
CFRAME06_REG CFU frame 6 control and status Std reg 0xF12D_C000 0xF12D_CFFF 4 KB  
CFRAME06_FDRI CFU frame 6 data register input (FDRI) Std port 0xF12D_D000 0xF12D_DFFF 4 KB  
CFRAME07_REG CFU frame 7 control and status Std reg 0xF12D_E000 0xF12D_EFFF 4 KB  
CFRAME07_FDRI CFU frame 7 data register input (FDRI) Std port 0xF12D_F000 0xF12D_FFFF 4 KB  
CFRAME08_REG CFU frame 8 control and status Std reg 0xF12E_0000 0xF12E_0FFF 4 KB  
CFRAME08_FDRI CFU frame 8 data register input (FDRI) Std port 0xF12E_1000 0xF12E_1FFF 4 KB  
CFRAME09_REG CFU frame 9 control and status Std reg 0xF12E_2000 0xF12E_2FFF 4 KB  
CFRAME09_FDRI CFU frame 9 data register input (FDRI) Std port 0xF12E_3000 0xF12E_3FFF 4 KB  
CFRAME10_REG CFU frame 10 control and status Std reg 0xF12E_4000 0xF12E_4FFF 4 KB  
CFRAME10_FDRI CFU frame 10 data register input (FDRI) Std port 0xF12E_5000 0xF12E_5FFF 4 KB  
CFRAME11_REG CFU frame 11 control and status Std reg 0xF12E_6000 0xF12E_6FFF 4 KB  
CFRAME11_FDRI CFU frame 11 data register input (FDRI) Std port 0xF12E_7000 0xF12E_7FFF 4 KB  
CFRAME12_REG CFU frame 12 control and status Std reg 0xF12E_8000 0xF12E_8FFF 4 KB  
CFRAME12_FDRI CFU frame 12 data register input (FDRI) Std port 0xF12E_9000 0xF12E_9FFF 4 KB  
CFRAME13_REG CFU frame 13 control and status Std reg 0xF12E_A000 0xF12E_AFFF 4 KB  
CFRAME13_FDRI CFU frame 13 data register input (FDRI) Std port 0xF12E_B000 0xF12E_BFFF 4 KB  
CFRAME14_REG CFU frame 14 control and status Std reg 0xF12E_C000 0xF12E_CFFF 4 KB  
CFRAME14_FDRI CFU frame 14 data register input (FDRI) Std port 0xF12E_D000 0xF12E_DFFF 4 KB  
CFRAME_BCAST_REG CFU frame broadcast control and status Std reg 0xF12E_E000 0xF12E_EFFF 4 KB  
CFRAME_BCAST_FDRI CFU frame broadcast data register input (FDRI) Std port 0xF12E_F000 0xF12E_FFFF 4 KB  
PMC_RAM_XMPU PMC memory protection unit to PMC RAM Std reg 0xF12F_0000 0xF12F_FFFF 64 KB  
PMC_NPI_XPPU PMC NPI controller peripheral protection unit (XMPU) Std reg 0xF130_0000 0xF130_FFFF 64 KB  
PMC_INT_XPPU PMC peripheral protection unit (XMPU) Std reg 0xF131_0000 0xF131_FFFF 64 KB  
PMC_INT_GPV PMC interconnect global programmers view (GPV) Std reg 0xF132_0000 0xF132_FFFF 64 KB  
PMC_SBI_XMPU PMC SBI memory protection unit Std reg 0xF133_0000 0xF133_FFFF 64 KB  
PMC_CFU_XMPU PMC CFU memory protection unit Std reg 0xF134_0000 0xF134_FFFF 64 KB  
PMC_INT_CSR PMC interconnect control and status Std reg 0xF140_0000 0xF160_FFFF 3 MB  
PMC_SHA2 SHA controller NDA reg 0xF180_0000 0xF180_FFFF 64 KB  
PMC_SLCR_SECURE PMC secure system level control registers Std reg 0xF190_0000 0xF190_FFFF 64 KB  
UART0 UART controller 0 Std reg 0xF192_0000 0xF192_FFFF 64 KB  
UART1 UART controller 1 Std reg 0xF193_0000 0xF193_FFFF 64 KB  
LPD_I3C0 LPD I3C controller 0 Std reg 0xF194_0000 0xF194_FFFF 64 KB  
LPD_I3C1 LPD I3C controller 1 Std reg 0xF195_0000 0xF195_FFFF 64 KB  
LPD_I3C2 LPD I3C controller 2 Std reg 0xF196_0000   64 KB  
LPD_I3C3 LPD I3C controller 3 Std reg 0xF197_0000   64 KB  
LPD_I3C4 LPD I3C controller 4 Std reg 0xF198_0000   64 KB  
LPD_I3C5 LPD I3C controller 5 Std reg 0xF199_0000   64 KB  
LPD_I3C6 LPD I3C controller 6 Std reg 0xF19A_0000   64 KB  
LPD_I3C7 LPD I3C controller 7 Std reg 0xF19B_0000   64 KB  
SPI0 SPI controller 0 Std reg 0xF19C_0000 0xF196_FFFF 64 KB  
SPI1 SPI controller 1 Std reg 0xF19D_0000 0xF197_FFFF 64 KB  
CANFD0 CAN flexible data rate controller 0 Std reg 0xF19E_0000 0xF198_FFFF 64 KB  
CANFD1 CAN flexible data rate controller 1 Std reg 0xF19F_0000 0xF199_FFFF 64 KB  
CANFD2 CAN flexible data rate controller 2 Std reg 0xF1A0_0000   64 KB  
CANFD3 CAN flexible data rate controller 3 Std reg 0xF1A1_0000   64 KB  
LPD_IOP_SLCR LPD IOP system level control Std reg 0xF1A2_0000 0xF19B_FFFF 128 KB  
LPD_IOP_SLCR_SECURE LPD IOP secure system level control Std reg 0xF1A4_0000 0xF19C_FFFF 64 KB  
LPD_GPIO PS LPD GPIO controller Std reg 0xF1A5_0000 0xF19D_FFFF 64 KB  
GEM0 GEM controller 0 Std reg 0xF1A6_0000 0xF19E_FFFF 64 KB  
GEM1 GEM controller 1 Std reg 0xF1A7_0000 0xF19F_FFFF 64 KB  
LPD_IOP_INT_GPV LPD IOP interconnect global programmers view (GPV) Std reg 0xF1A8_0000 0xF1AF_FFFF 512 MB  
USB0_XHCI USB 2.0 controller 0 XHCI Std reg 0xF1B0_0000 0xF1BF_FFFF 1 MB  
USB1_XHCI USB 2.0 controller 1 XHCI Std reg 0xF1C0_0000 0xF1CF_FFFF 1 MB  
LPD_IOP_INT_CSR LPD IOP interconnect control and status Std reg 0xF1D0_0000 0xF1D8_FFFF 704 KB  
TTC0 LPD Triple Timer Counter 0 Std reg 0xF1E6_0000 0xF1E6_FFFF 64 KB  
TTC1 LPD Triple Timer Counter 1 Std reg 0xF1E7_0000 0xF1E7_FFFF 64 KB  
TTC2 LPD Triple Timer Counter 2 Std reg 0xF1E8_0000 0xF1E8_FFFF 64 KB  
TTC3 LPD Triple Timer Counter 3 Std reg 0xF1E9_0000 0xF1E9_FFFF 64 KB  
TTC4 LPD Triple Timer Counter 4 Std reg 0xF1EA_0000 0xF1EA_FFFF 64 KB  
TTC5 LPD Triple Timer Counter 5 Std reg 0xF1EB_0000 0xF1EB_FFFF 64 KB  
TTC6 LPD Triple Timer Counter 6 Std reg 0xF1EC_0000 0xF1EC_FFFF 64 KB  
TTC7 LPD Triple Timer Counter 7 Std reg 0xF1ED_0000 0xF1ED_FFFF 64 KB  
USB0_CSR USB 2.0 controller 0 control and status Std reg 0xF1EE_0000 0xF1EE_FFFF 64 KB  
USB1_CSR USB 2.0 controller 1 control and status Std reg 0xF1EF_0000 0xF1EF_FFFF 64 KB  
CFU_STREAM CFU stream 1 Std mmap 0xF1F8_0000 0xF1F8_FFFF 256 KB  
PMC_RAM_mem PMC RAM memory space (for PLM use) Std mmap 0xF200_0000 0xF201_FFFF 128 KB  
PMC_SBI_mem PMC SBI memory space Std mmap 0xF210_0000 0xF210_FFFF 64 KB PMC_SBI_XMPU
NPI Registers NPI registers for NoC interfaces and I/O PHY and transceiver control and status Std reg 0xF600_0000 0xF7FF_FFFF 32 MB  
FPD_AXI_CMN_mem PSX CMN to FPD interface (HN-D port D) Std mmap 0xF800_0000 0xFBFF_FFFF 64 MB FPD_CMN_XMPU