Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026) - Describes the hardware aspects of the AMD Versal™ AI Edge Series Gen 2 and Prime Series Gen 2. - AM026
Document ID
AM026
Release Date
2025-12-23
Revision
1.3 English
Introduction
Introduction to Versal Adaptive SoCs
SoC Hardware Overview
Features
Subsystem Overviews
Block Diagram
Interconnect Features
System Performance Features
Software Programming
Software Environments
Embedded Microprocessor Code
Processor-to-processor Communications
Documentation
Technical Reference Manual Outline
Documentation Note about this TRM
Hardware Architecture
Device-level Interconnect Diagrams
Adaptive SoC Interconnect Diagram
APU Subsystem
APU Interconnect Diagram
APU Functional Units
RPU Subsystem
RPU Interconnect Diagram
RPU Functional Units
PMC Subsystem
Platform Management and Control
Features
PMC Block Diagram
PMC Interconnect Diagram
PMC Interconnect Components
PMC Functional Units
PMC I/O Signals
ASU Subsystem
Features
ASU Interconnect Diagram
ASU Subsystem Functional Units
NoC, DDRMC, PL Subsystems
NoC Interconnect
DDR Memory Controller
Programmable Logic
Configurable Logic Block
Digital Signal Processor
Block RAM
UltraRAM
Integrated Hardware Device Options
Hardware Accelerator
AI Engine
Graphics Processing Unit
Image Signal Processor and Video Codec Unit
Image Signal Processor
Video Codec Unit
PS High-speed Connectivity
Overview Diagram
Connectivity Modules
Device I/O Connectivity
MIO and Dedicated I/O Banks
I/O Buffer Pin Banks
Test and Debug
Platform Boot, Control, and Status
Overview
Non-Secure Boot Flow
Secure Boot Flow
Asymmetric Hardware Root of Trust Secure Boot
Configuration Update
Configuration Update with Key Revocation
PPK Revocation
SPK Revocation
Revocation as a Tamper Penalty
Symmetric Hardware Root of Trust Secure Boot
Configuration Update
Configuration Update with Partition Revocation
Boot Image
PDI Size Estimation
Boot Modes and Interfaces
Primary Boot Interfaces Table
Boot Search Limit
MIO Boot Interfaces
MIO Boot Interface Pin Buffer Settings
Boot Interface Signals
Dedicated Boot Signals
JTAG Boot Mode
OSPI Flash Boot Mode
OSPI Flash Boot Sequences
OSPI Flash Boot Commands
OSPI Flash Device Interface
OSPI Flash Boot Register Settings
QSPI Flash Boot Mode
QSPI Flash Boot Sequences
QSPI Flash Boot Commands
QSPI Flash Boot Interface
SD Flash Boot Mode
SD Flash Boot Interface
eMMC v5.1 Boot Mode
eMMC v5.1 Flash Boot Interface
eMMC Boot Register Settings
SelectMAP Boot Mode
SelectMAP Bus Width Detect Pattern Bit Order
SelectMAP Sequence
SelectMAP Boot Register Settings
SelectMAP Boot Mode Signals
Single Device Interface
Multiple Device Interface
Ganged Device Interface
SBI for JTAG and SelectMAP
Configuration Frame Unit
Configuration Frame Unit
Configuration Frame Interface
Platform Management
Functional Safety Management
Single Point Fault Detection
Common Cause Failure Detection
Latent Fault Detection
Isolation Features
Additional Features
Dynamic Function eXchange
Power Management
Security Management
Tamper Monitoring and Response
Secure Key Storage and Management
Key Selection
Battery-Backed RAM Key
eFUSE Key
Key Update Register
Boot Header Key
Storing Keys in Encrypted Form (Black)
Physically Unclonable Function
Key Management Summary
User Access to Hardware Cryptographic Accelerators
System Error Management
Platform Hardware Reference
Hardware Boot Events
PL-PMC GPI and GPO Port Signals
Device Identification
Address Maps and Programming Interfaces
Address Maps
4 GB Processor System Address Map
256 TB NoC Interconnect Address Map
Programming and Configuration Interfaces
APB and AXI Programming Interfaces
NPI Programming Interface
CFU Controller Programming Interface
Signals, Interfaces, Pins, and Controls
Dedicated Pins
Multiplexed I/O Signal Pins
MIO-at-a-Glance Tables
PMC MIO Pin Tables
LPD MIO Pin Table
MIO Routing Considerations
MIO-EMIO Interface Routing Options
MIO Pin Buffer Controls
Input Buffer Control Registers
Output Buffer Control Registers
MIO Pin Routing
MIO Routing Diagram
MIO Routing Functionality Details
MIO Pin Programming Example
PCIe Resets on MIO Pins
Processor and DMA Units
Application Processing Unit
Features
System Perspective
APU Cache Coherent Block Diagram
Lockstep CPU Cores
Real-time Processing Unit
Features
System Perspective
RPU Subsystem Block Diagram
RPU CPU Cluster
Tightly-coupled Memories
LPD DMA Controller
Features
LPD DMA Implementations
System Perspective
Block Diagram
Functional Units
Common Buffer
System Interfaces
AXI Read Arbiter
AXI Write Arbiter
Memory Coherency
PL Flow Control Interface
Programming Guide
Channel Block Diagram
Modes and States
Simple Mode Programming
Sequence Steps
Descriptor Mode Programming
Data Flow
Model
Buffer Descriptor Format
Descriptor Format
Linked List Mode Use Case
Linear Descriptor Use Case
Linked-List Descriptor Use Case
Hybrid Descriptor Use Case
Buffer Descriptor Summary
Interrupt Handling
Done Interrupt Accounting
Over Fetch
Transaction Control
Outstanding Transactions
Rate Control
PL Flow-Control Interface
Flow-Control Interface Considerations
Flow-Control Programming Model
Attached to the SRC
Channel Reading from a Flow Controlling a PL Destination
Channel Writing to a Flow Controlling the PL Destination
Interrupts
Descriptions
Transaction Security
Channel Pause
Coming Out of Pause
Programming Model for Changing DMA Channel States
Channel Enabled
Channel Disabled
Register Reference
DMA Channel Registers
I/O Flow Control Signals
Graphic Processing Unit
GPU IP Architecture
Interfaces and Address Mapping
GPU Visualization and Partitioning
Pixel Formats
API Extension List
Embedded Processors and Security Units
Overview
RCU ROM Code Unit
Features
RCU Implementations
PPU MicroBlaze Processor
Features
PPU Implementations
Programming Model
Interrupts Associated with PPU
Errors Associated with PPU
Authenticated JTAG
Tamper Event Monitoring and Response System
PMC Register Reference
PMC Global Registers
PMC Local Registers
PMC DMA Units and Stream Switch
Overview
PMC DMA Features
PMC DMA Implementations
System Perspective
Block Diagram
Stream Switch Routes
Programming Interface
Interrupt Signal
Clock Signal
Reset Signal
AXI Stream Switch Interface Signals
Operations
SRC DMA Module Operation
DST DMA Module Operation
DMA Command FIFO
Programming Considerations
PMC DMA Registers
Security Units
Overview
PMC AES
Secure Hash Algorithms
RSA/ECC
True Random Number Generator
Physically Unclonable Function
Battery-Backed RAM
Interconnect
Overview
Features
Interconnect Implementations
FPD SMMU and Coherent Implementations
iPort and ePort Implementations
AXI Interconnect Implementations
AXI Switch Feature Implementations
UltraScale+ MPSoC versus Versal Adaptive SoC Comparisons
Memory Protection Unit Implementations
Peripheral Protection Unit Implementations
PMC IOP Interconnect Switch
System Perspective
Network On Chip
Register Module Programming Interfaces
Detailed Interconnect Diagram
Transaction Hosts and Their Attributes
Transaction Hosts
Address
Address Generation
Data
System Management ID
Features
SMID Implementations
SMID Summary Table
Programmable SMID Mechanism
TrustZone Security
Features
Architecture
Security Profiles
PL Security
TrustZone Profile
Quality of Service
Traffic Types
QoS Signal Generation
Safety Features
Poisoned Transaction
Transaction Routes
System Memory Coherent Route
Routing and Coherency Controls
NoC Path from PMC through to FPD and PL is Not Supported
Interconnect Switch Functionality
Switch Architecture
Conceptual Interconnect
Features
Switch Ingress Ports
iPort Protocol Integrity Checker
iPort Isolation
iPort Parity Unit
Switch Egress Ports
Interconnect ePort Timeout Units
ePort Reset
ePort Parity Unit
ePort Isolation
Interconnect Interface Protocols
PS Interfaces to/from the PL fabric
PS-to-PL AXI Fabric Interfaces
PL-to-PS AXI Fabric Interfaces
System Memory Management Unit
Features
SMMU TBU Instances
Address Translation Examples
Memory Protection Functionality
SMMU Register Reference
Cache Mesh Network
Cache Interconnect Implementation
Coherency System Diagram
Memory Space Protection
Types of Protection Units
TrustZone Security
Always-Secure Register Programming Interfaces
Use Case Example
Memory Protection Units
Features
Protection Operations
Error Handling
AXI Transaction Signals
Configuration
XMPU Register Reference
XMPU Register Set
XMPU Write Lock
Peripheral Protection Units
Features
XPPU Instances
System Perspective
Transaction Checking Operations
SMID Validation
SMID Register
Aperture Permission Checking
Permission and TrustZone Registers
Aperture Register Map
Errors
XPPU Register Reference
XPPU Register Set
XPPU Write Lockdown
Interrupts and Errors
System Interrupts
System Interrupt Controllers
Sensitivity
System Interrupts Table
System Interrupts
Inter-Processor Interrupts
Features
IPI Controller Implementations
System Perspective
IPI Agents
SMID Agent Profiles
Agent Communications
Interrupt Architecture
Register Reference and Address Map
Message Passing Architecture
Programming Examples
Send an IPI Communication
Receive an IPI Communication
System Errors
Error Sources
Error Accumulator Modules
Error Management
Types of Errors Reference
System Error Summary Tables
System Errors to PMC EAM
System Errors to PS EAM
Timers, Counters, and RTC
Real-Time Clock
Features
Counter Module
Calibration
RTC Accuracy
External Clock Crystal and Circuitry
Interfaces and Signals
System Timestamp
System Timestamp Counter Implementations
Triple-Timer Counters
Features
TTC Implementations
Block Diagram
Overflow Detection Functional Model
Interval Timing Functional Model
Event Timer Functional Model
TTC I/O Interface
TTC I/O Diagram
TTC I/O Signals
System Watchdog Timers
Features
Window Timer Applications
SWDT Implementations
System Perspective
SWDT Block Diagram
Programming Interface
Watchdog Timer Clock Periods
Signals to the Timer
Signals Generated by the Timer
Window Watchdog Timer Mode
Window Mode Features and Options
Windowed Basic Mode
Basic State Diagram
Basic Program Sequence Monitor
Basic Window Programming Sequence
Windowed Q&A Mode
Q&A State Diagram
Q&A Programming Sequence
Q&A Token Response Bits Table
Generic Watchdog Timer Mode
Generic Programming Sequence
Register Reference
System-Level Registers
SWDT I/O Interface
SWDT I/O Interface Signals
PS High-speed Connectivity
PS High-Speed Connectivity Signals and Interfaces
USB 3.2, DisplayPort, HDCP Subsystem
USB 3.2 DRD Controller
USB Data Flow
USB Programming Guide
USB Register Overview
DisplayPort TX 1.4 Controller
HDCP 2.3
USB3 PHY
Display Controller
Functional Description
Display Controller Interfaces and Modes of Operation
Display Controller Clocks
Video Interface
SDP Interface
Register Overview
Programming Considerations
MDB5,10G Ethernet MAC and Aurora HSDP
10G Ethernet MAC
Register Overview
Programming the Controller
DMA
RX and TX FIFO Interfaces to PL
PCIe Subsystem
Register Overview
Programming Topics
HSDP Interface
PS High-Speed Connectivity Clocking and Reset Subsystem
I/O Peripheral Controllers
CAN FD Controller
Features
CAN/CANFD Controller Implementations
System Perspective
Block Diagram
Object Layer
Logical Link Layer
MAC Transfer Layer
System Interface
System Signals
I/O Interface
Programming Model
Modes and States
Reset State
Mode Table
Mode Transition
Configuration Mode
Normal Mode
Sleep Mode
Snoop (Bus Monitoring) Mode
Loopback Modes
Protocol Exception Event State
Bus-Off Recovery State
Configuration Sequence
Message Transmission
Cancellation
Message Reception
Acceptance Filters
RX Buffer Usages
Disabled RX Buffer
Enabled RX Buffer
Register Reference
Control and Status
Message Space Data
System-level Control Registers
CAN FD Controller I/O Signals
Gigabit Ethernet MAC
Features
GEM Interface Implementations
System Perspective
Block Diagram
Functional Units
System Signals
GEM Clocks
Controller Reset
System Interrupts
System Error
System Interfaces
I/O Interfaces
I/O Block Diagram
Clocks
Timestamp Unit Clock
Programming Model
Modes and States
10/100/1000 Operating Modes
Memory Packet Descriptors
Descriptor Length
DMA AXI Transactions
Burst Transactions
Transaction Routing and Coherency
Transmit Dataflow
Packet Buffer TX Functionality
TX Packets
TX Descriptor Entry Words
TX Descriptor Processing
MAC Transmitter
TX Broadcast Frames
TX Pause Frame
Quantum Time Base
Receive Dataflow
RX Packets
RX Packet Flow Monitoring
RX Descriptor Words
RX Descriptor Processing
MAC Receiver
Filtering
Hash Addressing
Capture All Frames
RX Broadcast Frames
VLAN Support
Wake-on-LAN Support
Magic Packet Events
Address Resolution Protocol
Specific Address 1 Filter Match
Multicast Hash Filter Match
Precision Timestamp Unit
MAC Pause Frames
RX Pause Frames
PFC Priority-based Pause Frame
Disable Copy of Pause Frames
Checksum Hardware
RX Checksum Offload
TX Checksum Offload
Register Reference
Control and Status
Statistics
System-Level Registers
AXI Transaction Control
GEM I/O Signal Reference
RGMII Interface Signals via MIO
RMII Interface Signals via MIO
MDIO Interface Signals
Timestamp Unit Interface Signals
GPIO Controller
Features
GPIO Controller Implementations
System Perspective
Block Diagram
System Interface
System Signals
I/O Interface
Programming Model
Channel Block Diagram
Input Programming Model
Interrupt Programming Model
Output Programming Model
GPIO Registers
GPIO I/O Signals
MIO Signals
EMIO Signals
I3C Controller
I3C Features
I2C Features
I2C and I3C Controller Implementations
I3C Controller Implementation
System Perspective
I3C Controller Block Diagram
APB Programming Interface
I3C Controller System Signals
I2C Modes
I2C Programming Model
I3C Interrupts
I2C Interrupts
I2C Initiate Data Transfers
I2C Manager Read Using Polled Method
I2C Manager Read Using Interrupt Method
I2C Manager Write Using Interrupt Method
I2C Monitor Mode
I3C Controller Registers
I3C Control and Status Registers
I/O Interface Signals
SYSMON I2C Interface Signals
SPI Controller
Features
SPI Controller Implementation
System Perspective
Block Diagram
System Interface
System Signals
I/O Interface Overview
Programming Model Overview
Modes and States
Master Mode
Slave Mode
Data Loopback Mode
Functional Diagram
FIFOs
Data Transfer
SPI Registers
Controller Registers
System Level Registers
SPI Controller I/O Signals
UART Controller
Features
UART Controller Implementation
System Perspective
Block Diagram
System Signals
I/O Interface
Programming Model
Modes
UART Functionality
Block Diagram
Operations
System and Diagnostic Loopback Testing
Baud Rate Divider and Clock Dependencies
Transmit Character Frame
Hardware Flow Control
RTS Flow Control
CTS Flow Control
IrDA Functionality
Block Diagram
Transmit Encoder
Receive Decoder
Data Modulation
Interrupts
UART Registers
Controller Registers
SLCR Registers
Clock and Reset Registers
UART I/O Interface Signals
USB 2.0 Controller
Features
USB Controller Implementations
System Perspective
High-Level Block Diagram
System Interfaces
USB System Signals
Clocks
Controller Resets
System Interrupts
System Error Signal
I/O Interface
Power
Programming Model
Host Mode Data Structures
Register Reference
Controller Registers
XHCI Registers
Host Capabilities, Offset, and Operations Registers
Port Status, Control, Host Interrupter, Event Ring, and Doorbell Registers
Miscellaneous Control, Status, and Capabilities Registers
Miscellaneous Configuration, Control, and User Registers
Device and Command Registers
System-Level Registers
LPD System-Level Registers
PMC System-Level Registers
Clock and Reset Registers
USB I/O Interfaces
Port Indicator, Fault, and Power Select Signals
Flash Memory Controllers
eMMC v5.1 Controller
eMMC Features
eMMC Flash Interface
eMMC v5.1 Interface Diagram
Octal SPI Flash Memory Controller
Features
System Perspective
Block Diagram
Functional Units
System Interfaces
System Signals
I/O Interface
Programming Model
Access Modes
Memory Access Modes
Polling Feature
Start-up Sequences
Direct Access Mode
DMA Programming Model
DMA Features
Programming Steps
Source DMA
Destination DMA
Configuration Restrictions
Interrupts
Controller Interrupts
OSPI Flash Device Interface
OSPI Flash Interface Diagrams
OSPI Flash Interface Signals
Quad SPI Controller
Features
QSPI Controller Implementations
System Perspective
Block Diagram
Functionality
System Interfaces
System Signals
QSPI Clocks
QSPIx_CLK Loopback Feature
Controller Resets
System Interrupt
System Error
I/O Interface
Programming Model
Modes and States
Start-up
Reset
PIO Mode
DMA Mode
I/O Programming
Configurations
Clock Tap Control Settings
I/O Striping Function
Striping Programming Examples
Striping with Odd Byte Count
Command Words
Word Format
Immediate Data Field Usage
Programming
Programming Flowchart
DMA Data Transfer Length Examples
PIO Mode Programming Model
DMA Programming Model
Polling Programming Model
Register Reference
QSPI Controller Registers
QSPI System-Level Registers
QSPI Flash Device Interface
QSPI Flash Interface Diagrams
QSPI Flash Interface Signals
SD_eMMC Controller
Features
SD and eMMC Controller Implementations
System Perspective
Block Diagram
Functional Units
System Interfaces
System Signals
SD Clocks
Controller Reset
System Interrupts
System Errors
I/O Interfaces
Modes and States
Speed Modes
States
Main Functionality
Command Controller
Transmit Control Unit
Receive Control Unit
Timeout Control
Data Transfer Block Buffer
I/O Functionality
Card Detect
Voltage Level Shifter Interface
I/O Clock Functionality
Clock Block Diagram
Controller Clock Start-up
I/O Clocking Modes
I/O Clock Frequency Control Sequence
25 MHz I/O Clock Range
Low-speed Clock Control Settings
Clock Frequency Divider Register Settings
High-speed I/O Clocking
DLL Programming Model
High-speed Clock Control Settings
High-speed TX Clocking
High-Speed RX Clocking
Auto-tuning Unit in DLL
Manual DLL Programming Sequence
DLL Presets
DLL Programming Example
SD Commands
SD Command Response Registers
Register-driven DMA Mode
Descriptor-driven DMA Mode
SD Flash Interfaces
SD Flash Interface v2.0 Diagram
SD Flash Interface v3.0 Diagram
SD Flash Interface Signals
eMMC Interface
eMMC Interface Signals
UFS Host Controller
Features
UFS Host Controller Implementations
System Perspective
Block Diagram
UFS Host Controller Interface Signals
Clocks
Clocks
Clock Distribution
Clock Domain Diagram
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices