Overview - AM020

Versal Adaptive SoC AIE-ML Architecture Manual (AM020)

Document ID: AM020
Release Date: 2026-02-18
Revision: 1.5 English

Overview
Introduction to Versal Adaptive SoCs
Navigating Content by Design Process
Motivation to AIE-ML
AIE-ML Array Features
AIE-ML Array Overview
AIE-ML Array Hierarchy
Performance
Clocking Structure
Memory Error Handling
Task-Completion-Tokens
Sparsity
AIE-ML Tile Architecture
Memory-mapped AXI4 Interconnect
AXI4-Stream Interconnect
AIE-ML Tile Program Memory
AIE-ML Interfaces
AIE-ML Memory Module
Data Movement
AIE-ML to AIE-ML Data Communication via Local Memory
AIE-ML Tile to AIE-ML Tile Data Communication via Memory and DMA
AIE-ML Tile to AIE-ML Tile Data Communication via AXI4-Stream Interconnect
AIE-ML to PL Data Communication via Shared Memory
AIE-ML Data Movement with Memory Tiles
AIE-ML Debug
AIE-ML Trace and Profiling
Trace
Profiling (Performance Counters)
AIE-ML Events
AIE-ML Array Interface Architecture
AIE-ML Array Interface
Features of the AIE-ML Array Interface
Array Interface Memory-Mapped AXI4 Slave Interconnect
Array Interface DMA Memory-Mapped AXI4 Master Interface
Array Interface AXI4-Stream Interconnect
AIE-ML to Programmable Logic Interface
Stream Switch Buffering and Latency
AIE-ML to NoC Interface AXI-Stream
Interrupt Handling
AIE-ML Architecture
Functional Overview
Register Files
Instruction Fetch and Decode Unit
Load and Store Unit
Scalar Unit
Arithmetic Logic Unit and Scalar Functions
Vector Unit
Fixed-Point Vector Unit
Floating-Point Vector Unit
Register Move Functionality
AIE-ML Memory Tile Architecture
AIE-ML Memory Tile Overview and Features
AIE-ML Memory Tile Memory
AIE-ML Memory Tile DMA
AIE-ML Memory Tile Locks Module and Stream Switch
AIE-ML Configuration and Boot
AIE-ML Array Configuration
AIE-ML Boot Sequence
AIE-ML Array Reconfiguration
Key Differences between AI Engine and AIE-ML
AIE-ML Array Architecture
AIE-ML Tile Architecture
AIE-ML Processor
AIE-ML Memory Tile
AIE-ML Array Interface
Software Programmability
Summary
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

Back to home page