Each AIE-ML memory tile has 512 KB of memory as 16 banks of 32 KB. Each bank is 128 bits wide and 2k words deep. Each bank allows one read or one write every cycle and can be accessed by nine read interfaces and nine write interfaces. Each interface is 128-bit. The following block diagrams show the memory tile read and write interfaces.
The interfaces also have the following features:
- Read Interfaces
- Memory-mapped AXI4 write including control packets for memory tile –1 and memory tile +1, and six MM2S channels [0-5]
- Write Interfaces
- Memory-mapped AXI4 read including control packets for memory tile –1 and memory tile +1, and six S2MM channels [0-5]
DMA S2MM channels (0 – 3) and MM2S channels (0 – 3) can access the local memory banks and the memory banks of the memory tile to the east and the west.
The memory in memory tile supports bank interleaving. Interleaving is done at a 128-bit granularity, such that sequential 128-bit accesses map to different banks and wrap around after the 16 banks, every 256B.
The memory tile banks have ECC protection and ECC scrubbing similar to the AIE-ML data memory.