The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 09/05/2024 Version 1.1 | |
| Features | Updated NRZ and PAM4 modulation rates. |
| Input Mode | Replaced MGTAVCC with VCM. |
| Reference Clock Selection and Distribution | Updated line rates. |
| LC Tank PLL |
|
| Dynamic Frac-N | Added section. |
| Transceiver RX Component Reset | Added note. |
| Table 1 | Updated PCSRESETMASK bit definitions. |
| Figure 2 | Added figure. |
| Ports and Attributes | Added clarification about attributes. |
| Power Down and PLL Power Down | Updated LCPLLPD to be attribute controlled. |
| TX and RX Power Down | Added information about half density mode. |
| Loopback | Added note about BER degradation. |
| Fabric Configuration Interface | Added information about TXOUTCLK. |
| Usage Mode | Clarified APB3ADDR settings for reads. |
| Digital Monitor | Added clarification of digital monitor clock source. |
| Table 3 | Added table. |
| Reading TX FIFO Latency | Added information about TXLATCLK. |
| TX Pattern Generator | Clarified PRBS patterns for PAM4 and added Table 2. |
| Figure 2 and Figure 1 | Added figures. |
| Table 1 | |
| Table 1, Table 1, Table 1, and Table 1 | Updated emphasis values. |
| Table 1 |
|
| Table 2 | Added table. |
| RX Analog Front End | Added sentence about level shifter circuit to first paragraph. |
| Figure 1 | Added RXRECCLKOUT to RX PROG DIV. |
| RX Margin Analysis | Updated sentence about implementing sample eye diagram. |
| Reading RX FIFO Latency | Added information on RXLATCLK. |
| Table 3 | Added table. |
| Table 1 |
|
| Figure 1 | Added VCCINT_GT. |
| Reference Clock |
|
| GTM Transceiver Reference Clock Checklist | Removed nominal range from second bullet. |
| Table 1 |
|
| 04/27/2022 Version 1.0 | |
| Initial release. | N/A |