Dynamic Frac-N

Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017)
Document ID
AM017
Release Date
2024-09-05
Revision
1.1 English

Typically, SDM*DATA is statically set to create a static fractional-N divider, but it is possible to continually update the value of SDM*DATA. The following figure shows how to use the GTM transceiver when dynamic Frac-N is required. Because dynamic Frac-N operates using LCPLLs, there is no independent PPM control for the lanes connected to a particular LCPLL.

Figure 1. Dynamic Frac-N Example

The operation of the dynamic fractional divider has a user-operated strobe (SDM*TOGGLE) pulse that controls the SDM*DATA transfer from the fabric to the transceiver. The assumption here is the logic that drives SDM*TOGGLE and SDM*DATA is clocked by SYSTEM clock.

The following figures show the same operation with different relationships between LCPLL FBCLK and SYSTEM clock frequencies.

Figure 2. FBCLK is Faster than SYSTEM Clock

Figure 3. FBCLK is Slower than SYSTEM Clock

There are three major timing requirements marked as T1, T2, and T3 in the two figures above. These timing requirements are described in the following table.

Table 1. Timing Requirements
Time Period Requirements Comments
T1 *≥* One system clock cycle This is the least amount of time SDM*DATA must be stable and valid before SDM*TOGGLE can be asserted. Period T1 should be at least one SYSTEM clock cycle. During this preiod, SDM*TOGGLE must be Low.
T2 *≥* Three FBCLK cycles This is the least amount of time SDM*TOGGLE must be held High. Period T2 should be at least three FBCLK cycles. SDM*DATA must not change during T2.
T3 *≥* Three FBCLK cycles This is the least amount of time SDM*TOGGLE must be held Low. Period T3 should be at least three FBCLK cycles. SDM*DATA must not change during T3. T3 does not include T1.
Note:
  1. The * symbol indicates either 0 or 1. For example, SDM*DATA can be SDM0DATA or SDM1DATA.
  2. USRCLK or ABPCLK can be used as the SYSTEM clock.
  3. Line rates should be below 29.0 Gb/s (NRZ) and 112.0 Gb/s (PAM4), or the frequency derivation should remain within a maximum of ± 100 ppm in both directions or 200 ppm in a single direction.

The following table shows the requirements for FBDIV when using the fractional-N divider.

Table 2. FBDIV Settings in Frac-N Mode
Frac-N Mode Line Rate (Gb/s) Integer Value Fractional Value
PAM4 19 – 58 N ≤ 80 0.1 ≤ FractionalPart ≤ 0.9
76 – 112 N ≤ 21 0.1 ≤ FractionalPart ≤ 0.9
NRZ 9.5 – 29 N ≤ 80 0.1 ≤ FractionalPart ≤ 0.9