CCIX VC1 Configuration Interface - CCIX VC1 Configuration Interface - AM016

Versal ACAP CPM CCIX Architecture Manual (AM016)
Document ID
AM016
Release Date
2020-11-24
Revision
1.1 English

The CCIX VC1 configuration is described in the following table.

Table 1. CCIX VC1 Configuration Interface
Name Direction Width Description
cfg_vc1_enable Output 1
  • Configuration VC1 Enable: VC1 Resource
  • Register: VC
  • Enable bit:
    • 1: Software has enabled VC1 operation
    • 0: VC1 disabled
cfg_vc1_negotiation_pending Output 1
  • Configuration VC1 Negotiation Pending: VC1 Resource Status
  • Register: VC Negotiation Pending bit
    • Asserted when active High
    • VC1 negotiation (initialization or disabling) is in the pending state
cfg_ccix_edr_data_rate_change_req Output 1

This signal is asserted (active-High) before entry into the EDR 20 GT/s or 25 GT/s data rate. When asserted, the user design must drain all pending TLPs on both VC0 and VC1 data paths. The signal is deasserted in response to the assertion of cfg_ccix_edr_data_rate_change_ack. This signal must be kept asserted until cfg_ccix_edr_data_rate_change_req is deasserted.
cfg_ccix_edr_data_rate_change_ack Input 1

This signal is asserted (active-High) by the user design in response to the assertion of cfg_ccix_edr_data_rate_change_req after all pending TLPs are drained on both the VC0 and VC1 data paths. This signal must be kept asserted until
cfg_edr_enable Output 1

This signal reflects the state of Physical Function #0, CCIX Transport