The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 10/31/2025 Version 1.8 | |
| Table 1 | Removed unused package types (NBVA1024, NSVE1369, NSVI1369) and updated LSC ball grid sizes (VSVA1596, VSRA1596, VSRC1596). |
| User I/O Pins by Device Package | Corrected the MIO values for the 2VM3558, 2VM3858, 2VE3504, 2VE3558, 2VE3804, 2VE3858 devices. |
| Table 2 | Updated the I/O banks for the SSVA1440 and SSVA2112 packages. |
| Device Diagrams Overview | Updated the I/O bank notes in Figure 1. |
| Bank Diagram by Package for VP1202 | Revised the VP1202-VSVA2785 note. The previous guidance that specified NC for the power pins corresponding to the LN power group should not be followed. |
| Figure 1 | Revised the X5IO bank information. |
| Figure 1 | Revised the X5IO bank information. |
| Figure 2 | Revised the X5IO bank information. |
| VIRA1596 Mechanical—XQVC1902 | Remove reference to another device in this package. |
| Packing and Shipping | Added packages and values. |
| Stencil | Updated details about the corner spacer. |
| 6/27/2025 Version 1.7 | |
| General updates | Added Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices throughout document. Added additional Pin Definitions. |
| PMCMIO, LPDMIO, PMCDIO Pin Definitions | Updated guide because the DONE pin is in the output direction. |
| Transceiver Footprint Compatibility Between Packages | Removed unbonded banks from VP2502 devices in VSRB3340 and VSVB3340 packages. |
| Die Level Bank Numbering Overview | Added X5IO information to the I/O Banks section. |
| ASCII Pinout Files | Updated links |
| Device Diagrams Overview | Updated the example diagram. |
| Peak Package Reflow Temperatures | Added XQ packages and reflow temperatures. |
| Pin Maps | Updated the RSVD pins in the following pin maps: |
| 12/09/2024 Version 1.6 | |
| General updates | Added the VM2152 device in the NFVD1024 and NFVM1369 packages throughout the document. |
|
Added ruggedized packages throughout the document (SBRA484, SSRA784, NSRG1369, SBRJ1369, VIRA1596, VSRA1596, VSRC1596, VSRD1760, VSRA2197, VSRA2785, VSRA3340, VSRB3340). |
|
| Table 1 | Added ruggedized packages. |
| Gigabit Transceiver Channels by Device/Package | Added ruggedized packages. |
| User I/O Pins by Device Package | Added ruggedized packages. |
| SelectIO Pin Definitions | Added XCC information. |
| Table 1 | Added VCC_SOC_SENSE and GND_VCC_SOC_SENSE pins. |
| Footprint Compatibility Between Packages | Added ruggedized packages to each table. |
| VC1902 Bank Diagram Overview and Bank Diagram by Package for VC1902 | Combined XQVC1902 with VC1902. |
| VM1802 Bank Diagram Overview and Bank Diagram by Package for VM1802 | Combined XQVM1802 with VM1802. |
| Bank Diagram by Package for VP1902 | Updated XY coordinate names on the overview and subsequent diagrams (by package). |
| VSVA2785 Mechanical—VP1202 | Updated image. |
| Packing and Shipping | Added ruggedized packages. |
| Edge Bonding Implementation | Updated Figure 1. |
| 7/02/2024 Version 1.5 | |
| General updates | Added the SBVJ1369 package for the XCVP1052 device throughout. |
| VSVB3340 package is updated for the XCVP2502. | |
| Device/Package Combinations | Updated Table 1. |
| VE2202 Bank Diagram Overview | Added diagram. |
| Bank Diagram by Package for VE2202 | Added diagram. |
| VC1502 Bank Diagram Overview | Updated the GTY Quad banks for the VC1502. |
| VP1902 Bank Diagram Overview | Added SLR region numbers to each XY coordinate. |
| Bank Diagram by Package for VP1902 | Added SLR region numbers to each XY coordinate for both the VSVA6865 and VSVB6865. |
| NSVH1369 Package—VE2802 Pin Map | Replaced with correct pin map. |
| NSVH1369 Package—VM2202 Pin Map | Updated pin map. |
| VSVA3340 Mechanical—VP1402 | Updated mechanical drawing. Added VSRA3340 package. |
| VSVA3340 Mechanical—VP1502 | Updated mechanical drawing. Added VSRA3340 package. |
| VSVA3340 Mechanical—VP1552 | Updated mechanical drawing. |
| VSVA3340 Mechanical—VP1702 | Updated mechanical drawing. Added VSRA3340 package. |
| VSVA5601 Mechanical—VP1802 | Updated mechanical drawing, incorrect pin names on the bottom view. |
| VSVA5601 Mechanical—VP2802 | Updated mechanical drawing, incorrect pin names on the bottom view. |
| Package Marking | Added the AMD Versal™ device package marking figures. |
| Peak Package Reflow Temperatures | Updated the table with packages and removed Note 1 because the data sheets do not contain more information. |
| Edge Bonding Implementation | Updated Figure 1. |
| Edge Bonding Guidelines | Added discussion on strain gauge measurements. |
| Edge Bonding Implementation | Updated guidelines using Zymet UA 2605 B edge-bonding material. |
| 9/28/2023 Version 1.4 | |
| General updates |
|
| SelectIO Pin Definitions | Updated the C4CIO_PAD description. |
| Power Pin Definitions | Updated the RSVD pin descriptions and added RSVD_VCCINT_SENSE, RSVD_GND_SENSE, and RSVD_VCCINT_GT pins. |
| PMCMIO, LPDMIO, PMCDIO Pin Definitions | Added Note 1. |
| Die Level Bank Numbering and Device Diagrams | Added additional diagrams. |
| Bank Diagram by Package for VP1202 | Added a note before figure Figure 2 and updated GTM Quad 206 to CG [LN] in the VSVA2785 package. |
| About ASCII Package Files | Updated the XPIO/GTMPerf description. |
| ASCII Pinout Files | Added Note 1 and Note 2 to the table. |
| Pin Maps | Added additional diagrams. Updated the LSVA4737 Package—VH1542 Pin Map, LSVA4737 Package—VH1582 Pin Map, LSVA4737 Package—VH1742 Pin Map, and LSVA4737 Package—VH1782 Pin Map. |
| SFVA784 and SSRA784 Packages—VM1102 Pin Map | Updated power pin legend for RSVD_VCCINT_SENSE and RSVD_GND_SENSE. |
| VSRA2197 Package—VM1502 Pin Map | Added pin map. |
| Mechanical Drawings | Added mechanical drawings. |
| VFVC1596 Mechanical—VM1302 and VM1402 | Updated drawing. |
| NSVH1369 Mechanical—VM2202, VC2602, VC2802, VE2602, and VE2802 | Updated drawing and added VM2202 support. |
| Stencil | Added more examples and Figure 3, Figure 2, and Table 1. |
| Edge Bonding Implementation | Updated Figure 1. |
| 3/23/2023 Version 1.3 | |
| General updates |
|
| SelectIO Pin Definitions | Added the C4CCIO_PAD pin. |
| Power Pin Definitions | Added the VCCINT_IO_HBM, VCC_HBM, and VCCAUX_HBM pins. |
| Pin Maps | Added VFVF1760 pin maps. |
| Table 8 | Removed die flatness and parallelism specifications for all lidless packages. |
| VSVA2785 Mechanical—VP1202 | Replaced with correct image. |
| Stencil | Updated to add both uniform and non-uniform stencil aperture design. |
| Edge Bonding Implementation | Updated both edge-bonding adhesive placement parameters. |
| 11/17/2022 Version 1.2 | |
| General updates | Added VSVA5601 package. Removed the VSVC2197 package (VM2202, VM2502, VP1202). Changed VFVH1760 package to VSVH1760 for VC2602, VC2802, VE2602, VE2802. |
| SelectIO Pin Definitions | Updated table for XCVN3716 devices including X5IO pins. |
| Power Pin Definitions | Added GND_SENSE and VCCINT_SENSE to the table. |
| Power Pin Definitions | Added VCCAUX_PLL, VCC_FPD, VCC_LPD, VCCAUX_LPD, VCC_HNICX |
| PMCMIO, LPDMIO, PMCDIO Pin Definitions | Added I3CI2C_SCL, I3CI2C_SDA, and a note to the REF_CLK description. |
| PMCMIO, LPDMIO, PMCDIO Pin Definitions | Added a note to the REF_CLK description. |
| Die Level Bank Numbering and Device Diagrams | Added additional diagrams to this chapter. |
| VM1102 Bank Diagram Overview | Revised diagrams including Bank Diagram by Package for VM1102. |
| About ASCII Package Files | Added an Important note about schematic symbols. |
| Pin Maps | Updated the section with additional pin maps. |
| Mechanical Drawings | Added reference to the 3D CAD STEP models. Updated the section with additional drawings and replaced the LSVC4072 Mechanical—VP1802 figure. |
| Packing and Shipping | Added values to the table and corrected the VSVB2197. |
| 7/05/2022 Version 1.1 | |
| General updates | Significant data realignment throughout document |
| Replaced the SFVB625 package with the SFVA784 package for the VM1102 throughout | |
| Added XQ devices | |
| Die Level Bank Numbering and Device Diagrams | Added bank diagrams for VC1352, VC1502, VC1702, VM1102, VM1302, VM1402, VM1502, VM2502, and VM2902 |
| I/O Bank Footprint Compatibility between Packages | Updated banks and added devices |
| Transceiver Footprint Compatibility Between Packages | Updated and added devices to the tables in this section |
| ASCII Pinout Files | Added links to the AMD Versal™ device package pinout files. |
| VSVD1760 Package—VM1802 Pin Map | Updated image for clarity |
| Mechanical Drawings | Updated the VIVA1596 Mechanical—VC1802 and VC1902, VFVC1760 Mechanical—VM1502 and VM1802, VSVA2197 Mechanical—VC1802, VC1902, and VM1802 |
| Added A4 dimension and VSRD1760 designation to VSVD1760 Mechanical—VC1802, VC1902, and VM1802 | |
| Package Marking | Added marking for XQ AMD Versal™ devices |
| Soldering Guidelines | Updated jpj1554077106995.html#jpj1554077106995__note_import_rework |
| Stencil | Updated Figure 1 |
| Edge Bonding Implementation | Updated table and images |
| Edge Bond Removal | Updated discussion |
| Conformal Coating | Moved section |
| Guidelines for Thermal Interface Materials | Updated the recommendation and added a table |
| 7/16/2020 Version 1.0 | |
| Initial release. | N/A |