This section lists the differences from previous generations of the packaging and pinout specifications.
- In addition to 0.8 mm and 1.0 mm BGA ball pitch, AMD Versal™ device packages have 0.92 mm BGA ball pitch, signified by a package code beginning with a V or an N.
- Some packages include land-side capacitor (LSC) technology (decoupling capacitors on the bottom side of the package, adjacent to the BGA balls). Mechanical Drawings contains the LSC array dimensions for each package.
- Versal devices have XPIO, PMCMIO, and LPDMIO hardware blocks bonded to package pins.
- I/Os in some banks on the left and right edges of the XPIO and X5IO rows lack direct access to all I/O logic resources. Use these banks only for DDR memory controller (DDRMC) applications.
- Each row of XPIO banks has a single IO_VR pin. This replaces the VRP pins previously found in each HPIO bank.
- VCCO voltage range for XPIO banks is 1.0V to 1.5V instead of the 1.0V to 1.8V range for HPIO banks in previous generations.
- Previously separated into I/O diagrams and power/dedicated/multifunction diagrams, the Versal device diagrams combine package pinout details into a single diagram.
- A 2D bar code replaces package markings found in previous device generations.