Banking and Clocking Summary
For each device, not all banks are bonded out in every package.
GTY and GTM Columns
- One GT Quad = Four transceivers = Four GTYE5_QUAD or GTME5_QUAD primitives.
- Not all GT Quads are bonded out in every package.
- Also shown are quads labeled with RCAL. This specifies the location of the RCAL masters for each device. With respect to the package, the RCAL masters are located on the same package pin for each package, regardless of the device.
- The XY coordinates shown in each quad correspond to the transceiver channel number found in the pin names for that quad (as shown in the next section).
- An alphabetic designator is shown in each quad. Each letter corresponds to the columns in the tables in the Transceiver Footprint Compatibility Between Packages section.
- The power supply group is shown in brackets [ ] for each quad.
I/O Banks
- Each user XPIO bank has a total of 54 I/Os that can be used as differential (27 differential pairs) or single-ended I/Os. All 54 pads of a bank are not always bonded out to pins.
- A limited number of XPIO banks have fewer than 54 SelectIO pins. These banks are shown in gray (partially).
- Each user X5IO bank has a total of 32 I/Os that can be used as differential (16 differential pairs) or single-ended I/Os. All 32 pads of a bank are not always bonded out to pins.
- A limited number of X5IO banks have fewer than 32 SelectIO pins. These banks are shown in gray (partially).
- Each user HDIO bank has a total of 22 I/Os that can be used as pseudo-differential (11 differential pairs) or single-ended I/Os.
- Adjacent to each bank is a physical layer (PHY) containing clock buffers and clock management resources
- XPIO and X5IO banks are arranged in rows on the north and south of the device with adjacent PHY and clock management resources.
- XPIO and X5IO banks are separated into groups of 1, 2, or 3 banks that signify how to group them when used for DDR memory controller applications.
- I/Os in some banks on the left and right edges of the XPIO and X5IO rows do not have direct access to all I/O logic resources and can only be used for DDR memory controller (DDRMC) applications. These I/Os are specified in the following device diagrams, where each XPIO or X5IO bank is designated by a Y (DDRMC only) or a N (access to all I/O logic resources) for each nibble (nine nibbles per bank and six XPIOs per nibble) or octads (four octads per bank and eight X5IOs per octad). This is also specified in the DDRMC Only column of the Package Files.
- Some boundary logic interface blocks (BLIs) provide access to the NoC via a NoC master unit (NMU). X5IO octads designated by an S (NO_NMU_SHARED) for each octad (four octads per bank and eight X5IOs per octad) have access to the programmable logic (PL), but the BLI resources are shared with an NMU. As a result, the NMU access point that shares a pin's BLI is unavailable when used as an I/O. This is also specified in the DDRMC Only column of the Package Files.
- Global clock (GC) pins in DDRMC Only nibbles/octads include full access to clock management resources.
- HDIO banks are arranged in columns and separated into rows that are pitch-matched with adjacent PHY, clock management resources, and GT blocks.
- An alphabetic designator is shown in each bank. Each letter corresponds to the columns in Table 1.
Clocking
- Each XPIO bank has four pairs of global clock (GC) inputs for four differential or four single-ended clock inputs. Single-ended clock inputs should be connected to the P-side of the differential pair.
- Each X5IO bank has one pairs of global clock (GC) inputs for one differential or one single-ended clock inputs. Single-ended clock inputs needs to be connected to the P-side of the differential pair.
- Each HDIO bank has two P-N pairs of global clock (HDGC) input pins. When used as a clock input, each P-N pair of global clock input pins can support a pseudo-differential pair, a true-differential pair, or a single-ended clock input that must be connected to the P-side of the pair. A limited selection of I/O standards are supported for HDGC clock inputs.
- Clock signals are distributed through global buffers driving routing and distribution networks to reach any clock region, I/O, or GTY transceivers.
- Global clock inputs can connect to MMCMs and PLLs within the XPIO or X5IO bank or adjacent clock management resources
Processor Blocks
- PMC MIO pins are in banks 500 and 501
- LPD MIO pins are in bank 502
- PMC dedicated pins are in bank 500 and 503
Integrated Blocks
- PCIe
- Integrated block for PCIe® . The PCIe blocks with an additional (Tandem) label support tandem configuration.
- CPM
- CCIX and PCIe processor sub-system module
- ILKN
- Interlaken block
- MRMAC
- 100G multirate Ethernet MAC
- DCMAC
- 600G channelized multirate Ethernet subsystem
- Accelerator RAM (XRAM)
- On-chip memory
- DRAM
- DDR memory
- HBM
- High bandwidth memory
- HSC
- High-speed cryptography block
- PS High-speed connectivity
- Includes GTR transceiver in the PS, USB 3.2, DisplayPort 1.4
- ISP
- Image signal processor
- VCU
- Video codec unit
- VDU
- Video decoder unit
- UFS 3.1
- M-PHY controller interface