Banking and Clocking Summary
For each device, not all banks are bonded out in every package.
GTY and GTM Columns
- One GT Quad = Four transceivers = Four GTYE5_QUAD or GTME5_QUAD primitives.
- Not all GT Quads are bonded out in every package.
- Also shown are quads labeled with RCAL. This specifies the location of the RCAL masters for each device. With respect to the package, the RCAL masters are located on the same package pin for each package, regardless of the device.
- The XY coordinates for each quad match the transceiver channel number in its pin names (shown in the next section).
- An alphabetic designator is shown in each quad. Each letter corresponds to the columns in the tables in the Transceiver Footprint Compatibility Between Packages section.
- The power supply group is shown in brackets [ ] for each quad.
I/O Banks
- Each user XPIO bank has a total of 54 I/Os that can be used as differential (27 differential pairs) or single-ended I/Os. All 54 pads of a bank are not always bonded out to pins.
- A limited number of XPIO banks have fewer than 54 SelectIO pins. These banks are shown in gray (partially).
- Each user X5IO bank has a total of 32 I/Os that can be used as differential (16 differential pairs) or single-ended I/Os. All 32 pads of a bank are not always bonded out to pins.
- A limited number of X5IO banks have fewer than 32 SelectIO pins. These banks are shown in gray (partially).
- Each user HDIO bank has a total of 22 I/Os that can be used as pseudo-differential (11 differential pairs) or single-ended I/Os.
- Adjacent to each bank is a physical layer (PHY) containing clock buffers and clock management resources
- XPIO and X5IO banks are arranged in rows on the north and south of the device with adjacent PHY and clock management resources.
- XPIO and X5IO banks are in groups of 1, 2, or 3 banks that signify the groups to use for DDR memory controller applications.
- I/Os in some banks on the left and right edges of the XPIO and X5IO rows lack direct access to all I/O logic resources. Use these banks only for DDR memory controller (DDRMC) applications. These I/Os are specified in the following device diagrams. For each XPIO or X5IO bank, each nibble or octad is marked Y or N. Y means DDRMC-only access. N means access to all I/O logic resources. Each bank has nine nibbles with six XPIOs per nibble, or four octads with eight X5IOs per octad. This is in the Package Files under the DDRMC Only column.
- Some boundary logic interface blocks (BLIs) connect to the NoC through a NoC master unit (NMU). In X5IO banks, an octad marked S (NO_NMU_SHARED) still accesses programmable logic (PL), but shares BLI resources with an NMU. When an I/O uses a shared BLI pin, the corresponding NMU access point is unavailable. This is in the Package Files under the DDRMC Only column.
- Global clock (GC) pins in DDRMC Only nibbles/octads include full access to clock management resources.
- HDIO banks are arranged in columns and separated into rows that are pitch-matched with adjacent PHY, clock management resources, and GT blocks.
- An alphabetic designator is shown in each bank. Each letter corresponds to the columns in Table 1.
Clocking
- Each XPIO bank has four pairs of global clock (GC) inputs for four differential or four single-ended clock inputs. Connect single-ended clock inputs to the P-side of the differential pair.
- Each X5IO bank has one global clock input pair for one differential or one single-ended clock input. Connect single-ended clock inputs to the P-side of the differential pair.
- Each HDIO bank has two P-N pairs of global clock (HDGC) input pins. Each pair supports pseudo-differential, true-differential, or single-ended clock input when used as a clock input. For single-ended input, connect the clock to the P-side of the pair. HDGC clock inputs support only a limited selection of I/O standards.
- Global buffers distribute clock signals through routing and distribution networks to any clock region, I/O, or GTY transceiver.
- Global clock inputs can connect to MMCMs and PLLs within the XPIO or X5IO bank or adjacent clock management resources.
Processor Blocks
- PMC MIO pins are in banks 500 and 501
- LPD MIO pins are in bank 502
- PMC dedicated pins are in bank 500 and 503
Integrated Blocks
- PCIe
- Integrated block for PCIe® . The PCIe blocks with an additional (Tandem) label support tandem configuration.
- CPM
- CCIX and PCIe processor sub-system module
- ILKN
- Interlaken block
- MRMAC
- 100G multirate Ethernet MAC
- DCMAC
- 600G channelized multirate Ethernet subsystem
- Accelerator RAM (XRAM)
- On-chip memory
- DRAM
- DDR memory
- HBM
- High bandwidth memory
- HSC
- High-speed cryptography block
- PS High-speed connectivity
- Includes GTR transceiver in the PS, USB 3.2, DisplayPort 1.4
- ISP
- Image signal processor
- VCU
- Video codec unit
- VDU
- Video decoder unit
- UFS 3.1
- M-PHY controller interface