The ASCII package files for each AMD Versal™ device includes a comma-separated-values (CSV) version and a text version optimized for a browser or text editor in fixed-width fonts. The information in each of the files includes:
- Header with device/package name (family-device-package), date and time of creation, package specification designator, and revision history
- Seven columns containing data for each pin:
- Pin—Pin location on the package
- Pin Name—The name of the assigned pin
- Bank—Bank number
- I/O Type—HDIO, XPIO, X5IO, GTY, GTYP, GTM, PMCMIO, PMCDIO, or LPDMIO depends on the I/O type.
- Super logic region (SLR) number for SSI devices (not applicable for monolithic devices).
- XPIO/GTMPerf:
- For XPIO pins, performance (HIGH, MEDIUM, or LOW) that the LPDDR4 interfaces are specified. See the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) for more information.
- For GTM pins, performance (HIGH or MEDIUM) that the GTM channels are specified for 112G long-reach applications. See the Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017) for more information.
- See the device data sheet for the performance definitions of each specification.
- DDRMC Only—For XPIO and X5IO pins:
- YES specifies that the pin is supported for use in DDR memory applications only and does not include full access to I/O logic resources.
- YES_PLUS_GC specifies the pin is supported for use in DDR memory applications and additionally has full access to clock management resources.
- NO specifies the pin has full access to I/O logic resources.
- NO_NMU_SHARED (for X5IO pins) specifies the pin shares logic resources with an NMU.
- Total number of pins in the package
Important: Schematic symbols can vary
depending on the schematic entry tool and are therefore not provided for Versal devices. Designers are expected to use the package
files detailed here to create their own schematic symbols in the desired format.