zFx_TPHR_CAP_NEXTPTR_3 (CPM4_PCIE0_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

zFx_TPHR_CAP_NEXTPTR_3 (CPM4_PCIE0_ATTR) Register Description

Register NamezFx_TPHR_CAP_NEXTPTR_3
Offset Address0x0000000930
Absolute Address 0x00FCA50930 (CPM4_PCIE0_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionTPHR Next Capability Offset: Bits 31:20 TPHR Extended Capability Header Register. Only lower 8 bits are in use.

This register should only be written to during reset of the PCIe block

zFx_TPHR_CAP_NEXTPTR_3 (CPM4_PCIE0_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr11:0rwNormal read/write0x0