zFx_PCIE_CAP_NEXTPTR_0 (CPM5_PCIE_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

zFx_PCIE_CAP_NEXTPTR_0 (CPM5_PCIE_ATTR) Register Description

Register NamezFx_PCIE_CAP_NEXTPTR_0
Offset Address0x0000000D14
Absolute Address 0x00FCE08D14 (CPM5_PCIE0_ATTR)
0x00FCE88D14 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPCIe
Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.

This register should only be written to during reset of the PCIe block

zFx_PCIE_CAP_NEXTPTR_0 (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 7:0rwNormal read/write0x0