zFx_ATS_CAP_INV_QUEUE_DEPTH_5 (CPM5_PCIE_ATTR) Register - zFx_ATS_CAP_INV_QUEUE_DEPTH_5 (CPM5_PCIE_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document_ID
AM012
Release_Date
2026-08-24
Revision
1.6

zFx_ATS_CAP_INV_QUEUE_DEPTH_5 (CPM5_PCIE_ATTR) Register Description

Register NamezFx_ATS_CAP_INV_QUEUE_DEPTH_5
Offset Address0x0000001B60
Absolute Address 0x00FCE09B60 (CPM5_PCIE0_ATTR)
0x00FCE89B60 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionATS Capability Invalidate Queue Depth
VFG* attributes are UNUSED

This register should only be written to during reset of the PCIe block

zFx_ATS_CAP_INV_QUEUE_DEPTH_5 (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 4:0rwNormal read/write0x0ATS Capability Invalidate Queue Depth
VFG* attributes are UNUSED