zFx_ATS_CAP_INV_QUEUE_DEPTH_5 (CPM4_PCIE0_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

zFx_ATS_CAP_INV_QUEUE_DEPTH_5 (CPM4_PCIE0_ATTR) Register Description

Register NamezFx_ATS_CAP_INV_QUEUE_DEPTH_5
Offset Address0x00000009D8
Absolute Address 0x00FCA509D8 (CPM4_PCIE0_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionATS Capability Invalidate Queue Depth
VFG* attributes are UNUSED

This register should only be written to during reset of the PCIe block

zFx_ATS_CAP_INV_QUEUE_DEPTH_5 (CPM4_PCIE0_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 4:0rwNormal read/write0x0