ps_cpm_pcie_axi_power_main_ResilienceFaultController_LatentFault0 (CPM5_INT_GPV) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

ps_cpm_pcie_axi_power_main_ResilienceFaultController_LatentFault0 (CPM5_INT_GPV) Register Description

Register Nameps_cpm_pcie_axi_power_main_ResilienceFaultController_LatentFault0
Offset Address0x0000002018
Absolute Address 0x00FCD82018 (CPM5_INT_GPV)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionRegister LatentFault0

Alternate register name: if_ps_cpm_pcie_axi_power_main_ResilienceFaultController_LatentFault0

ps_cpm_pcie_axi_power_main_ResilienceFaultController_LatentFault0 (CPM5_INT_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LatentFault031:0roRead-only0x0LatentFault0 register