por_mxp_errctlr_NS_u_smxp_0_1 (CPM5_CMN600) Register - AM012

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2025-09-25
Revision
1.5

por_mxp_errctlr_NS_u_smxp_0_1 (CPM5_CMN600) Register Description

Register Namepor_mxp_errctlr_NS_u_smxp_0_1
Offset Address0x000010B108
Absolute Address 0x00FC10B108 (CPM5_CMN)
Width64
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionFunctions as the non-secure error control register. Controls whether specific error-handling interrupts and error detection/deferment are enabled.

por_mxp_errctlr_NS_u_smxp_0_1 (CPM5_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved63:9razRead as zero0x0reserved
CFI 8rwNormal read/write0x0Enables corrected error interrupt as specified in por_mxp_errfr_NS.CFI
Reserved 7:4razRead as zero0x0reserved
FI 3rwNormal read/write0x0Enables fault handling interrupt for all detected deferred errors as specified in por_mxp_errfr_NS.FI
UI 2rwNormal read/write0x0Enables uncorrected error interrupt as specified in por_mxp_errfr_NS.UI
DE 1rwNormal read/write0x0Enables error deferment as specified in por_mxp_errfr_NS.DE
ED 0rwNormal read/write0x0Enables error detection as specified in por_mxp_errfr_NS.ED