por_hnf_errfr_u_hnf_nid40 (CPM5_CMN600) Register - por_hnf_errfr_u_hnf_nid40 (CPM5_CMN600) Register

por_hnf_errfr_u_hnf_nid40 (CPM5_CMN600) Register Description

Register Name	por_hnf_errfr_u_hnf_nid40
Offset Address	0x0000503000
Absolute Address	0x00FC503000 (CPM5_CMN)
Width	64
Type	mixedMixed types. See bit-field details.
Reset Value	0x000048A5
Description	Functions as the error feature register.

Field Name	Bits	Type	Reset Value	Description
Reserved	63:15	razRead as zero	0x0	reserved
CEC	14:12	roRead-only	0x4	Standard corrected error count mechanism 3b000: Does not implement standardized error counter model 3b010: Implements 8-bit error counter in por_hnf_errmisc[39:32] 3b100: Implements 16-bit error counter in por_hnf_errmisc[47:32]
CFI	11:10	roRead-only	0x2	Corrected error interrupt
Reserved	9:8	razRead as zero	0x0	reserved
FI	7:6	roRead-only	0x2	Fault handling interrupt
UI	5:4	roRead-only	0x2	Uncorrected error interrupt
DE	3:2	roRead-only	0x1	Deferred errors for data poison
ED	1:0	roRead-only	0x1	Error detection