por_dt_trace_control_u_hnd_nid8 (CPM4_CMN600) Register Description
| Register Name | por_dt_trace_control_u_hnd_nid8 |
|---|---|
| Offset Address | 0x0000130A30 |
| Absolute Address | 0x00FC130A30 (CPM4_CMN) |
| Width | 64 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Functions as the trace control register. |
por_dt_trace_control_u_hnd_nid8 (CPM4_CMN600) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 63:9 | razRead as zero | 0x0 | reserved |
| cc_enable | 8 | rwNormal read/write | 0x0 | Cycle count enable |
| timestamp_period | 7:5 | rwNormal read/write | 0x0 | Time stamp packet insertion period 3b000: Time stamp disabled 3b011: Time stamp every 8K clock cycles 3b100: Time stamp every 16K clock cycles 3b101: Time stamp every 32K clock cycles 3b110: Time stamp every 64K clock cycles |
| async_period | 4:0 | rwNormal read/write | 0x0 | Alignment sync packet insertion period 5h00: Alignment sync disabled 5h08: Alignment sync inserted after 256B of trace 5h09: Alignment sync inserted after 512B of trace 5h14: Alignment sync inserted after 1048576B of trace NOTE: All other values are reserved. |