| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 63:31 | razRead as zero | 0x0 | reserved |
| pmevcnt3_global_num | 30:28 | rwNormal read/write | 0x0 | Global counter to pair with PMU counter 3; see pmevcnt0_global_num for encodings |
| Reserved | 27 | razRead as zero | 0x0 | reserved |
| pmevcnt2_global_num | 26:24 | rwNormal read/write | 0x0 | Global counter to pair with PMU counter 2; see pmevcnt0_global_num for encodings |
| Reserved | 23 | razRead as zero | 0x0 | reserved |
| pmevcnt1_global_num | 22:20 | rwNormal read/write | 0x0 | Global counter to pair with PMU counter 1; see pmevcnt0_global_num for encodings |
| Reserved | 19 | razRead as zero | 0x0 | reserved |
| pmevcnt0_global_num | 18:16 | rwNormal read/write | 0x0 | Global counter to pair with PMU counter 0 3b000: Global PMU event counter A 3b001: Global PMU event counter B 3b010: Global PMU event counter C 3b011: Global PMU event counter D 3b100: Global PMU event counter E 3b101: Global PMU event counter F 3b110: Global PMU event counter G 3b111: Global PMU event counter H |
| Reserved | 15:9 | razRead as zero | 0x0 | reserved |
| cntr_rst | 8 | rwNormal read/write | 0x0 | Enables clearing of live counters upon assertion of snapshot |
| pmevcnt_paired | 7:4 | rwNormal read/write | 0x0 | PMU local counter paired with global counter |
| pmevcntall_combined | 3 | rwNormal read/write | 0x0 | Enables combination of all PMU counters (0, 1, 2, 3) NOTE: When set, pmevcnt01_combined and pmevcnt23_combined have no effect. |
| pmevcnt23_combined | 2 | rwNormal read/write | 0x0 | Enables combination of PMU counters 2 and 3 |
| pmevcnt01_combined | 1 | rwNormal read/write | 0x0 | Enables combination of PMU counters 0 and 1 |
| pmu_en | 0 | rwNormal read/write | 0x0 | CXLA PMU enable NOTE: All other fields in this register are valid only if this bit is set. |