por_cxla_pmevcnt_u_cxrh_nid72 (CPM5_CMN600) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

por_cxla_pmevcnt_u_cxrh_nid72 (CPM5_CMN600) Register Description

Register Namepor_cxla_pmevcnt_u_cxrh_nid72
Offset Address0x0000922220
Absolute Address 0x00FC922220 (CPM5_CMN)
Width64
TyperwNormal read/write
Reset Value0x00000000
DescriptionContains all PMU event counters (0, 1, 2, 3).

por_cxla_pmevcnt_u_cxrh_nid72 (CPM5_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
pmevcnt363:48rwNormal read/write0x0PMU event counter 3
pmevcnt247:32rwNormal read/write0x0PMU event counter 2
pmevcnt131:16rwNormal read/write0x0PMU event counter 1
pmevcnt015:0rwNormal read/write0x0PMU event counter 0