dma0_intcpm_axi_wr_I_main_QosGenerator_Id_CoreId (CPM5_INT_GPV) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

dma0_intcpm_axi_wr_I_main_QosGenerator_Id_CoreId (CPM5_INT_GPV) Register Description

Register Namedma0_intcpm_axi_wr_I_main_QosGenerator_Id_CoreId
Offset Address0x0000000480
Absolute Address 0x00FCD80480 (CPM5_INT_GPV)
Width32
TyperoRead-only
Reset Value0xBB462204
DescriptionStores the Core Id and its checksum.

Alternate register name: if_dma0_intcpm_axi_wr_I_main_QosGenerator_Id_CoreId

dma0_intcpm_axi_wr_I_main_QosGenerator_Id_CoreId (CPM5_INT_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CoreChecksum31:8roRead-only0xBB4622Field containing a checksum of the parameters of the IP.
CoreTypeId 7:0roRead-only0x4Field identifying the type of IP.