ccix_per_pkt_hdr_0 (CPM4_DVSEC0) Register - ccix_per_pkt_hdr_0 (CPM4_DVSEC0) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2025-09-25
Revision
1.5

ccix_per_pkt_hdr_0 (CPM4_DVSEC0) Register Description

Register Nameccix_per_pkt_hdr_0
Offset Address0x0000000DCC
Absolute Address 0x00FCFB0DCC (CPM4_DVSEC0)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCCIX PER Message Capability (Physical Function #0 only)

ccix_per_pkt_hdr_0 (CPM4_DVSEC0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
byte031:24rwNormal read/write0x0Packet Header Byte 0
byte123:16rwNormal read/write0x0Packet Header Byte 1
byte215:8rwNormal read/write0x0Packet Header Byte 2
byte3 7:0rwNormal read/write0x0Packet Header Byte 3