ccix_per_control (CPM5_DVSEC) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

ccix_per_control (CPM5_DVSEC) Register Description

Register Nameccix_per_control
Offset Address0x0000000DC8
Absolute Address 0x00FCE40DC8 (CPM5_DVSEC0)
0x00FCEC0DC8 (CPM5_DVSEC1)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCCIX PER Message Capability (Physical Function #0 only)

ccix_per_control (CPM5_DVSEC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0rwNormal read/write0x0Control Register