attr_dma_pf9_vf (CPM5_DMA_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

attr_dma_pf9_vf (CPM5_DMA_ATTR) Register Description

Register Nameattr_dma_pf9_vf
Offset Address0x0000000398
Absolute Address 0x00FCE10398 (CPM5_DMA0_ATTR)
0x00FCE90398 (CPM5_DMA1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPF VF Configuration

This register should only be written to during reset of the PCIe block

attr_dma_pf9_vf (CPM5_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
firstvf_offset25:13rwNormal read/write0x0the function offset to the 1st VF within the PF
num_vfs12:0rwNormal read/write0x0number of VFs assigned to a PF, when 0, the 1stvf_offset is invalid