attr_dma_pciebar2axibar_pf5_bar4_sec_cache_len_vf (CPM5_DMA_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

attr_dma_pciebar2axibar_pf5_bar4_sec_cache_len_vf (CPM5_DMA_ATTR) Register Description

Register Nameattr_dma_pciebar2axibar_pf5_bar4_sec_cache_len_vf
Offset Address0x00000004F0
Absolute Address 0x00FCE104F0 (CPM5_DMA0_ATTR)
0x00FCE904F0 (CPM5_DMA1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
Descriptionattr_dma_pciebar2axibar_pf5_bar4_sec_cache_len_vf

This register should only be written to during reset of the PCIe block

attr_dma_pciebar2axibar_pf5_bar4_sec_cache_len_vf (CPM5_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
len_vf16:10rwNormal read/write0x0Bar size in bits for PF[*] BAR