attr_dma_ch2_h2c_axi_dsc (CPM5_DMA_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

attr_dma_ch2_h2c_axi_dsc (CPM5_DMA_ATTR) Register Description

Register Nameattr_dma_ch2_h2c_axi_dsc
Offset Address0x0000000308
Absolute Address 0x00FCE10308 (CPM5_DMA0_ATTR)
0x00FCE90308 (CPM5_DMA1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionFetch descriptors from AXI MM interface

This register should only be written to during reset of the PCIe block

attr_dma_ch2_h2c_axi_dsc (CPM5_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0