attr_dma_axibar2pciebar_new_2_base_addr_h (CPM5_DMA_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

attr_dma_axibar2pciebar_new_2_base_addr_h (CPM5_DMA_ATTR) Register Description

Register Nameattr_dma_axibar2pciebar_new_2_base_addr_h
Offset Address0x0000000750
Absolute Address 0x00FCE10750 (CPM5_DMA0_ATTR)
0x00FCE90750 (CPM5_DMA1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
Descriptionattr_dma_axibar2pciebar_new_2_base_addr_h

attr_dma_axibar2pciebar_new_2_base_addr_h (CPM5_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr31:0rwNormal read/write0x0Bits [63:0] of the address