attr_dma_axibar2pciebar_new_0_base_addr_h (CPM5_DMA_ATTR) Register - attr_dma_axibar2pciebar_new_0_base_addr_h (CPM5_DMA_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document_ID
AM012
Release_Date
2026-08-24
Revision
1.6

attr_dma_axibar2pciebar_new_0_base_addr_h (CPM5_DMA_ATTR) Register Description

Register Nameattr_dma_axibar2pciebar_new_0_base_addr_h
Offset Address0x0000000738
Absolute Address 0x00FCE10738 (CPM5_DMA0_ATTR)
0x00FCE90738 (CPM5_DMA1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAttr Dma Axibar2Pciebar New 0 Base Addr H register

This register should only be written to during reset of the PCIe block

attr_dma_axibar2pciebar_new_0_base_addr_h (CPM5_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr31:0rwNormal read/write0x0Bits [63:0] of the address