agent_iccc0_llc_indirect_ram_cont_3 (CPM4_L2_CSR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

agent_iccc0_llc_indirect_ram_cont_3 (CPM4_L2_CSR) Register Description

Register Nameagent_iccc0_llc_indirect_ram_cont_3
Offset Address0x0000006158
Absolute Address 0x00FCD06158 (CPM4_L2_CSR)
Width64
TyperwNormal read/write
Reset Value0x00000000
DescriptionThis is the indirect access RAM content register.

This is the indirect access RAM content register. It is used in conjunction with the indirect access trigger register. On an indirect read, data is written to this register. On an indirect write, content from this register is written into the RAM. On a read-modify-write, content from this register is used for the XOR function. Since the RAM data width may be larger than 64 bits, multiple registers are used to hold the data. Any bits beyond the data width are unused. This register requires secure access, since it can be used to modify or observe the contents of data.

agent_iccc0_llc_indirect_ram_cont_3 (CPM4_L2_CSR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RAM_content63:0rwNormal read/write0x0