agent_iccc0_ccc_interrupt_err (CPM4_L2_CSR) Register Description
| Register Name | agent_iccc0_ccc_interrupt_err |
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| Offset Address | 0x0000004198 |
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| Absolute Address |
0x00FCD04198 (CPM4_L2_CSR)
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| Width | 64 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | This interrupt is a status register that tracks the interrupt generating events. |
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This interrupt is a status register that tracks the interrupt generating events. This includes multi-bit ECC error, single-bit ECC error, and event counter overflow. When these events occur, this register is updated and will hold the bit value until cleared. It can be cleared by writing to the register. To allow per-bit clearing control, the write value should use a value of 1 when it doesnt want to make a change, or a value of 0 when it wants to clear.
agent_iccc0_ccc_interrupt_err (CPM4_L2_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| UNSD_63_7 | 63:7 | roRead-only | 0x0 | |
| E6 | 6 | rwNormal read/write | 0x0 | 1b1: Prefetch buffer data parity error interrupt |
| E5 | 5 | rwNormal read/write | 0x0 | 1b1: Data parity error interrupt |
| E4 | 4 | rwNormal read/write | 0x0 | 1b1: Register parity error interrupt |
| E3 | 3 | rwNormal read/write | 0x0 | 1b1: Snoop Response interrupt status |
| E2 | 2 | rwNormal read/write | 0x0 | 1b1: Event counter overflow interrupt status |
| E1 | 1 | rwNormal read/write | 0x0 | 1b1: Single-bit error interrupt status |
| E0 | 0 | rwNormal read/write | 0x0 | 1b1: Multi-bit error interrupt status |