VGA_ISA_RW_DISABLE (CPM5_PCIE_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

VGA_ISA_RW_DISABLE (CPM5_PCIE_ATTR) Register Description

Register NameVGA_ISA_RW_DISABLE
Offset Address0x0000000978
Absolute Address 0x00FCE08978 (CPM5_PCIE0_ATTR)
0x00FCE88978 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionBridge Control Register VGA 16-Bit Decode, VGA Enable, ISA Enable R/W Disable: When TRUE, disables writing to the Bridge Control Register VGA 16-Bit Decode, VGA Enable, and ISA Enable register bits.
When FALSE, these 3 register bits are writable.

This register should only be written to during reset of the PCIe block

VGA_ISA_RW_DISABLE (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0