USR_IRQ_ACK (CPM4_XDMA_CSR) Register Description
| Register Name | USR_IRQ_ACK |
|---|---|
| Offset Address | 0x0000000E5C |
| Absolute Address | 0x00E1000E5C (CPM4_XDMA_CSR) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Register to allow the user application to access usr_irq_ack interface. This register is only implemented for End Point. For Root Port, reads return 0 and writes are ignored. |
USR_IRQ_ACK (CPM4_XDMA_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| usr_irq_fail | 31:16 | roRead-only | 0x0 | Indiates the value of usr_irq_fail. See DMA IRQ Block for the definition of usr_irq_fail. Bit[n] is only valid when usr_irq_ack[n] is set. |
| usr_irq_ack | 15:0 | roRead-only | 0x0 | Indiates the value of usr_irq_ack. See DMA IRQ Block for the definition of usr_irq_ack. Bit[n] is automatically cleared when usr_irq_req[i] is set for INTx/MSI/MSI-X or clear when usr_irq_req[i] is cleared for INTx. |