TPH_FROM_RAM_PIPELINE (CPM4_PCIE1_ATTR) Register Description
| Register Name | TPH_FROM_RAM_PIPELINE |
|---|---|
| Offset Address | 0x0000000980 |
| Absolute Address | 0x00FCA60980 (CPM4_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | TPH From RAM Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on BRAM to Hard Block path. FALSE indicates that there is no pipeline. |
This register should only be written to during reset of the PCIe block
TPH_FROM_RAM_PIPELINE (CPM4_PCIE1_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 |