TL_RX_CCIX_FIFO_TO_RAM_READ_PIPELINE (CPM5_PCIE_ATTR) Register Description
| Register Name | TL_RX_CCIX_FIFO_TO_RAM_READ_PIPELINE |
|---|---|
| Offset Address | 0x00000005F0 |
| Absolute Address |
0x00FCE085F0 (CPM5_PCIE0_ATTR) 0x00FCE885F0 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | TL to RX CCIX FIFO RAM Read Pipeline: If TRUE indicates presence of a external flip-flop pipeline stage on raddr, ren. FALSE indicates that there is no pipeline. Must be equal to TL_RX_CCIX_FIFO_TO_RAM_WRITE_PIPELINE selection. |
This register should only be written to during reset of the PCIe block
TL_RX_CCIX_FIFO_TO_RAM_READ_PIPELINE (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 |