TL_RX_CCIX_FIFO_FROM_RAM_READ_PIPELINE (CPM4_PCIE0_ATTR) Register Description
| Register Name | TL_RX_CCIX_FIFO_FROM_RAM_READ_PIPELINE |
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| Offset Address | 0x0000000408 |
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| Absolute Address |
0x00FCA50408 (CPM4_PCIE0_ATTR)
|
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| Width | 32 |
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| Type | rwNormal read/write |
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| Reset Value | 0x00000000 |
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| Description | RX CCIX FIFO RAM To TL Read Pipeline: If TRUE indicates presence of a external = flip-flop pipeline stage on rdata. FALSE indicates that there is no pipeline. |
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This register should only be written to during reset of the PCIe block
TL_RX_CCIX_FIFO_FROM_RAM_READ_PIPELINE (CPM4_PCIE0_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| attr | 0 | rwNormal read/write | 0x0 | attr |