TL_PF_ENABLE_REG (CPM5_PCIE_ATTR) Register Description
| Register Name | TL_PF_ENABLE_REG |
|---|---|
| Offset Address | 0x0000000564 |
| Absolute Address |
0x00FCE08564 (CPM5_PCIE0_ATTR) 0x00FCE88564 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Function Enable: 0000b = Function 0 Enabled. 0001b = Functions 0,1 Enabled. 0010b = Functions 0,1,2 Enabled. 0011b = Functions 0,1,2,3 Enabled. 0100b = Functions 0,1,2,3,4 Enabled. 0101b = Functions 0,1,2,3,4,5 Enabled. 0110b = Functions 0,1,2,3,4,5,6 Enabled. 0111b = Functions 0,1,2,3,4,5,6,7 Enabled. 1000b = Functions 0 - 8 Enabled (PCIeA5 Only). 1001b = Functions 0 - 9 Enabled (PCIeA5 Only). 1010b = Functions 0 - 10 Enabled (PCIeA5 Only). 1011b = Functions 0 - 11 Enabled (PCIeA5 Only). 1100b = Functions 0 - 12 Enabled (PCIeA5 Only). 1101b = Functions 0 - 13 Enabled (PCIeA5 Only). 1110b = Functions 0 - 14 Enabled (PCIeA5 Only). 1111b = Functions 0 - 15 Enabled (PCIeA5 Only). |
This register should only be written to during reset of the PCIe block
TL_PF_ENABLE_REG (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 3:0 | rwNormal read/write | 0x0 |