TL_FC_UPDATE_MIN_INTERVAL_TIME (CPM4_PCIE1_ATTR) Register Description
| Register Name | TL_FC_UPDATE_MIN_INTERVAL_TIME |
|---|---|
| Offset Address | 0x00000003F0 |
| Absolute Address | 0x00FCA603F0 (CPM4_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Transaction Tx Update FC Interval Timer: Expressed in units of 1us elapsed time and tracked independently for Posted, Non-Posted and Completion (if applicable) credit queues. An update FC is scehdule for transmission only after time indicated by valuye of TL_FC_UPDATE_MIN_INTERVAL_TIME[4:0] has elapsed after receeption of a TLP, and number of TLPs indicated by TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT[4:0] have not been received. Once an Update FC is scheduled for transimission, the internal timer is reset to start counting down from the value indicated by TL_FC_UPDATE_MIN_INTERVAL_TIME[4:0] and received TLP count is reset to start counting down from value indicated by TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT[4:0] (if enabled). Value of 0d indicates that the feature is disabled. |
This register should only be written to during reset of the PCIe block
TL_FC_UPDATE_MIN_INTERVAL_TIME (CPM4_PCIE1_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 4:0 | rwNormal read/write | 0x0 |