TL_DISABLE_RX_FLOW_CTL (CPM5_PCIE_ATTR) Register Description
| Register Name | TL_DISABLE_RX_FLOW_CTL |
|---|---|
| Offset Address | 0x00000005F8 |
| Absolute Address |
0x00FCE085F8 (CPM5_PCIE0_ATTR) 0x00FCE885F8 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Disable Rx Flow Control: When set to 1b, disables internal flow control credit return mechanism, and enables, the tl_rx_{posted,nonposted,completion}_*_released_* (user_spare_in interface). Sould be set to 0b for normal operation. |
This register should only be written to during reset of the PCIe block
TL_DISABLE_RX_FLOW_CTL (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 |