TEST_MODE_PIN_CHAR (CPM4_PCIE0_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2025-09-25
Revision
1.5

TEST_MODE_PIN_CHAR (CPM4_PCIE0_ATTR) Register Description

Register NameTEST_MODE_PIN_CHAR
Offset Address0x0000000BB8
Absolute Address 0x00FCA50BB8 (CPM4_PCIE0_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPin Characterization Test mode. When TRUE enable Input to Output paths for pin characterization. Note: pipe_txn/rxn_data[15:0] (only) are testable with the following configuration required: CRM_CORE_CLK_FREQ_500 = "FALSE", pipe_clk = 125MHz, core_clk = 250MHz.

This register should only be written to during reset of the PCIe block

TEST_MODE_PIN_CHAR (CPM4_PCIE0_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0